| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_cos_sin_mod.s | 40 STMFD SP!, {R4-R12, R14}
54 AND R12, R10, #7
55 CMP R12, #0
93 SMULWT R12, R1, R2
100 QSUB R12, R12, R6
106 STR R12, [R10, #4]
110 SMULWB R12, R1, R2
115 QSUB R12, R12, R6
122 STR R12, [R10, #0xF8]
127 SMULWT R12, R0, R2
[all …]
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| D | ixheaacd_enery_calc_per_subband.s | 34 SUB R12, R3, R2
83 LDR R12, [R8], #0x100
86 EOR R12, R12, R12, ASR #31
88 ORRGE R6, R6, R12
102 LDR R12, [R8], #0x100
106 MOV R12, R12, ASR R14
107 SMLABB R6, R12, R12, R6
113 RSB R12, R14, #0
119 MOV R4, R4, LSL R12
121 MOV R3, R3, LSL R12
[all …]
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| D | ixheaacd_sbr_qmfsyn64_winadd.s | 29 STMFD sp!, {R4-R12, R14}
36 MOV R12, R2
51 ADD R12, R12, R6
91 VLD1.16 D11, [R12]!
96 MOV R11, R12
98 ADD R12, R12, #248
101 VLD1.16 D13, [R12], R9
106 VLD1.16 D15, [R12], R9
111 VLD1.16 D17, [R12], R9
116 VLD1.16 D19, [R12], R9
[all …]
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| D | ixheaacd_esbr_qmfsyn64_winadd.s | 20 STMFD sp!, {R4-R12, R14}
26 MOV R12, R2
38 ADD R12, R12, R6
85 VLD1.32 {D2, D3}, [R12]!
87 MOV R11, R12
92 ADD R12, R12, #496
94 VLD1.32 {D6, D7}, [R12], R9
100 VLD1.32 {D10, D11}, [R12], R9
106 VLD1.32 {D14, D15}, [R12], R9
112 VLD1.32 {D18, D19}, [R12], R9
[all …]
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| D | ixheaacd_apply_rot.s | 27 STMFD SP!, {R4-R12, R14}
74 LDR R12, [R0, #44]
80 LDR R5, [R12]
82 LDR R6, [R12, #0x80]
94 STR R5, [R12], #4
96 STR R14, [R12, #0x7c]
98 LDR R5, [R12, #0x3c]
99 LDR R6, [R12, #0xbc]
111 STR R5, [R12, #0x3c]
113 STR R14, [R12, #0xbc]
[all …]
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| D | ixheaacd_conv_ergtoamplitudelp.s | 37 MOV R12, #0
52 LDRH R12, [R6, R5]
55 SMULWBNE R12, R12, R11
128 MOV R12, R12, LSL R6
129 CMP R12, #0x8000
130 MVNGE R12, #0x8000
131 CMNLT R12, #0x00008000
132 MOVLT R12, #0x00008000
133 STRH R12, [R2], #4
139 MOV R12, R12, ASR R6
[all …]
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| D | ixheaacd_overlap_add2.s | 28 STMFD sp!, {R4-R12, R14}
44 SUB R12, R5, #1
46 MOV R12, R12, LSL #2
48 ADD R7, R1, R12
53 MOV R12, #-16
54 VLD2.16 {D6, D7}, [R7], R12
70 VLD2.16 {D14, D15}, [R7], R12
83 VLD2.16 {D6, D7}, [R7], R12
104 VLD2.16 {D14, D15}, [R7], R12
132 MOV R12, #12
[all …]
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| D | ixheaacd_tns_parcor2lpc_32x16.s | 26 STMFD SP!, {R2, R4-R12, R14}
51 MOV R12, R3
67 SUBS R12, R12, #1
75 MOV R12, R3
95 SUBS R12, R12, #1
|
| D | ixheaacd_overlap_add1.s | 29 STMFD sp!, {R4-R12, R14}
43 MOV R12, #0
44 VDUP.S16 D12, R12
45 MOV R12, #-16
47 VLD1.32 {D6, D7}, [R10], R12
58 VLD2.16 {D2, D3}, [R8], R12
96 VLD1.32 {D6, D7}, [R10], R12
113 VLD2.16 {D2, D3}, [R8], R12
140 VLD1.32 {D6, D7}, [R10], R12
160 VLD2.16 {D2, D3}, [R8], R12
[all …]
|
| D | ixheaacd_conv_ergtoamplitude.s | 38 MOV R12, #0
51 LDRH R12, [R11, R5]
55 SMULWBNE R12, R12, R10
60 STRH R12, [R2, #-4]
|
| D | ixheaacd_post_twiddle_overlap.s | 28 STMFD sp!, {R4-R12}
65 SMULWB R12, R9, R10
68 SUB R8, R12, R11
73 MOV R12, #-50
75 SMULWB R11, R8, R12
87 SMULWT R12, R8, R10
109 MOVS R8, R12, ASR R9
111 MOVLT R12, #0x80000000
112 MVNGT R12, #0x80000000
113 MOVEQ R12, R12, LSL R11
[all …]
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| D | ia_xheaacd_mps_mulshift.s | 28 STMFD sp!, {R4-R12}
44 LDMFD sp!, {R4-R12}
|
| D | ixheaacd_calcmaxspectralline.s | 28 STMFD sp!, {R4-R12, R14}
77 LDMFD sp!, {R4-R12, R15}
|
| D | ixheaacd_dct3_32.s | 34 STMFD sp!, {R4-R12, R14}
50 MOV R12, #-16
55 VLD1.32 {Q1}, [R7], R12
72 VLD1.32 {Q4}, [R5], R12
87 VLD1.32 {Q1}, [R7], R12
117 VLD1.32 {Q4}, [R5], R12
263 MOV R12, #4
430 VLD1.16 D10, [R4], R12
|
| /external/libhevc/common/arm/ |
| D | ihevc_resi_trans_32x32_a9q.s | 124 MOV R12,#COFF_STD_2B_32
125 LSL R12,#3
127 VLD1.S32 D30[0],[R9],R12
128 VLD1.S32 D30[1],[R9],R12 @ D30 - [0 0] [0 1] [8 0] [8 1]
129 VLD1.S32 D31[0],[R9],R12
130 VLD1.S32 D31[1],[R9],R12 @ D31 - [16 0] [16 1] [24 0] [24 1]
156 @R12 ------
240 MOV R12,#COFF_STD_2B_32 @Get stride of coeffs
242 ADD R11,R9,R12,LSL #2 @Load address of g_ai2_ihevc_trans_32[4]
243 LSL R12,R12,#3
[all …]
|
| D | ihevc_resi_trans.s | 1023 MOV R12,#COFF_STD_2B
1024 LSL R12,#2
1026 VLD1.S32 D30[0],[R9],R12
1027 VLD1.S32 D30[1],[R9],R12
1028 VLD1.S32 D31[0],[R9],R12
1029 VLD1.S32 D31[1],[R9],R12
1055 @R12 ------
1158 MOV R12,#COFF_STD_2B @Get stride of coeffs
1165 ADD R11,R9,R12,LSL #1 @Load address of g_ai2_ihevc_trans_16[2]
1166 LSL R12,R12,#2
[all …]
|
| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 149 ; ALL: ll $[[R12:[0-9]+]], 0($[[R2]])
150 ; ALL: addu $[[R13:[0-9]+]], $[[R12]], $[[R9]]
152 ; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]]
159 ; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]]
194 ; ALL: ll $[[R12:[0-9]+]], 0($[[R2]])
195 ; ALL: subu $[[R13:[0-9]+]], $[[R12]], $[[R9]]
197 ; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]]
204 ; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]]
239 ; ALL: ll $[[R12:[0-9]+]], 0($[[R2]])
240 ; ALL: and $[[R13:[0-9]+]], $[[R12]], $[[R9]]
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/Hexagon/ |
| D | fmul-v67.ll | 15 ; CHECK: [[R12:(r[0-9]+:[0-9]+)]] = dfmpyll([[R10]],[[R11]])
16 ; CHECK: [[R12]] += dfmpylh([[R10]],[[R11]])
17 ; CHECK: [[R12]] += dfmpylh([[R11]],[[R10]])
18 ; CHECK: [[R12]] += dfmpyhh([[R10]],[[R11]])
|
| /external/swiftshader/third_party/marl/src/ |
| D | osfiber_asm_x64.h | 40 uintptr_t R12; member
60 static_assert(offsetof(marl_fiber_context, R12) == MARL_REG_R12,
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | 2010-03-09-indirect-call.ll | 5 ; Indirect calls must use R12 on Darwin (i.e., R12 must contain the address of
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430CallingConv.td | 19 // i16 are returned in registers R15, R14, R13, R12
20 CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430CallingConv.td | 18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
|
| /external/llvm-project/llvm/lib/Target/MSP430/ |
| D | MSP430CallingConv.td | 18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
|
| /external/llvm-project/llvm/lib/Target/ARC/ |
| D | ARCRegisterInfo.td | 42 def R12 : Core<12, "%r12">, DwarfRegNum<[12]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
78 (add R0, R1, R2, R3, R12, R13, R14, R15)>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCRegisterInfo.td | 42 def R12 : Core<12, "%r12">, DwarfRegNum<[12]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
78 (add R0, R1, R2, R3, R12, R13, R14, R15)>;
|