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Searched refs:R16 (Results 1 – 25 of 138) sorted by relevance

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/external/llvm/test/CodeGen/Mips/
Datomic.ll153 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
154 ; ALL: sc $[[R16]], 0($[[R2]])
155 ; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]]
156 ; MICROMIPS: beqzc $[[R16]], $[[BB0]]
157 ; MIPSR6: beqzc $[[R16]], $[[BB0]]
198 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
199 ; ALL: sc $[[R16]], 0($[[R2]])
200 ; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]]
201 ; MICROMIPS: beqzc $[[R16]], $[[BB0]]
202 ; MIPSR6: beqzc $[[R16]], $[[BB0]]
[all …]
/external/llvm-project/llvm/test/CodeGen/AVR/
Dsext.ll3 ; sext R17:R16, R13
18 ; sext R17:R16, R16
/external/mesa3d/src/gallium/drivers/zink/
Dzink_format.c29 MAP_FORMAT_NORM(R16)
30 MAP_FORMAT_SCALED(R16)
31 MAP_FORMAT_INT(R16)
32 MAP_FORMAT_FLOAT(R16)
/external/mesa3d/src/gallium/drivers/nouveau/nv50/
Dnv50_formats.c171 F3(A, L16_UNORM, R16_UNORM, R, R, R, xx, UNORM, R16, TC),
172 F3(A, L16_SNORM, R16_SNORM, R, R, R, xx, SNORM, R16, TC),
173 F3(A, L16_FLOAT, R16_FLOAT, R, R, R, xx, FLOAT, R16, TB),
174 I3(A, L16_SINT, R16_SINT, R, R, R, xx, SINT, R16, TR),
175 I3(A, L16_UINT, R16_UINT, R, R, R, xx, UINT, R16, TR),
184 C4(A, I16_UNORM, R16_UNORM, R, R, R, R, UNORM, R16, TR),
185 C4(A, I16_SNORM, R16_SNORM, R, R, R, R, SNORM, R16, TR),
186 C4(A, I16_FLOAT, R16_FLOAT, R, R, R, R, FLOAT, R16, TR),
187 C4(A, I16_SINT, R16_SINT, R, R, R, R, SINT, R16, TR),
188 C4(A, I16_UINT, R16_UINT, R, R, R, R, UINT, R16, TR),
[all …]
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dfunnel-shift2.ll6 ; CHECK: r[[R17:[0-9]+]]:[[R16:[0-9]+]] = combine
9 ; CHECK: r[[R1]]:[[R0]] |= lsr(r[[R17]]:[[R16]],#1)
/external/llvm-project/llvm/lib/Target/AVR/
DAVRRegisterInfo.td60 def R16 : AVRReg<16, "r16">, DwarfRegNum<[16]>;
97 def R17R16 : AVRReg<16, "r17:r16", [R16, R17]>, DwarfRegNum<[16]>;
113 def R16R15 : AVRReg<15, "r16:r15", [R15, R16]>, DwarfRegNum<[15]>;
131 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
149 R28, R29, R17, R16
155 add R23, R22, R21, R20, R19, R18, R17, R16
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td61 def R16 : AVRReg<16, "r16">, DwarfRegNum<[16]>;
98 def R17R16 : AVRReg<16, "r17:r16", [R16, R17]>, DwarfRegNum<[16]>;
123 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
141 R28, R29, R17, R16
147 add R23, R22, R21, R20, R19, R18, R17, R16
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRRegisterInfo.td60 def R16 : AVRReg<16, "r16">, DwarfRegNum<[16]>;
97 def R17R16 : AVRReg<16, "r17:r16", [R16, R17]>, DwarfRegNum<[16]>;
120 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
138 R28, R29, R17, R16
144 add R23, R22, R21, R20, R19, R18, R17, R16
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp51 return Hexagon::R16 <= Reg && Reg <= Hexagon::R27; in isCalleeSaveReg()
107 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
116 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
/external/mesa3d/src/gallium/drivers/v3d/
Dv3dx_format_table.c86 FORMAT(R16_UNORM, NO, R16, SWIZ_X001, 32, 1),
102 FORMAT(L16_UNORM, NO, R16, SWIZ_XXX1, 32, 1),
104 FORMAT(I16_UNORM, NO, R16, SWIZ_XXXX, 32, 1),
106 FORMAT(A16_UNORM, NO, R16, SWIZ_000X, 32, 1),
/external/llvm-project/llvm/lib/Target/ARC/
DARCRegisterInfo.td48 def R16 : Core<16, "%r16">, DwarfRegNum<[16]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCRegisterInfo.td48 def R16 : Core<16, "%r16">, DwarfRegNum<[16]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
/external/linux-kselftest/tools/testing/selftests/powerpc/stringloops/asm/
Dppc_asm.h17 #define R16 r16 macro
/external/angle/src/image_util/
Dimageformats.h244 struct R16 struct
248 static void readColor(gl::ColorF *dst, const R16 *src); argument
249 static void readColor(gl::ColorUI *dst, const R16 *src);
250 static void writeColor(R16 *dst, const gl::ColorF *src);
251 static void writeColor(R16 *dst, const gl::ColorUI *src);
252 static void average(R16 *dst, const R16 *src1, const R16 *src2);
/external/linux-kselftest/tools/testing/selftests/powerpc/copyloops/asm/
Dppc_asm.h12 #define R16 r16 macro
/external/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h81 case Lanai::R16: in getLanaiRegisterNumbering()
/external/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h82 case Lanai::R16: in getLanaiRegisterNumbering()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h81 case Lanai::R16: in getLanaiRegisterNumbering()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp109 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
118 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp109 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
118 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
/external/llvm-project/llvm/test/Transforms/LowerTypeTests/
Dsimple.ll67 ; CHECK: [[R16:%[^ ]*]] = phi i1 [ false, {{%[^ ]*}} ], [ [[R11]], {{%[^ ]*}} ]
73 ; CHECK: ret i1 [[R16]]
/external/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td47 (add R3, R9, R12, R13, R14, R16, R17,
/external/llvm-project/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td46 (add R3, R9, R12, R13, R14, R16, R17,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td46 (add R3, R9, R12, R13, R14, R16, R17,
/external/angle/src/libANGLE/renderer/
DFormat_table_autogen.cpp179 …ID::R16_UINT, GL_R16UI, GL_R16UI, GenerateMip<R16>, NoCopyFunctions, ReadColor<R16, GLuint>, Write…
180 …6_UNORM, GL_R16_EXT, GL_R16_EXT, GenerateMip<R16>, NoCopyFunctions, ReadColor<R16, GLfloat>, Write…
181 …ED_ANGLEX, GL_R16_USCALED_ANGLEX, GenerateMip<R16>, NoCopyFunctions, ReadColor<R16, GLuint>, Write…

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