Searched refs:RADEON_PP_CUBIC_OFFSET_T0_0 (Results 1 – 6 of 6) sorted by relevance
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_sanity.c | 142 { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" },
254 { RADEON_PP_CUBIC_OFFSET_T0_0, "RADEON_PP_CUBIC_OFFSET_T0_0" },
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| D | radeon_state_init.c | 140 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
442 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break; in cube_emit_cs()
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| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | r200_sanity.c | 146 { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" },
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| D | r200_state_init.c | 146 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
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| /external/mesa3d/src/mesa/drivers/dri/radeon/server/ |
| D | radeon_reg.h | 1340 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ macro
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| /external/mesa3d/src/mesa/drivers/dri/r200/server/ |
| D | radeon_reg.h | 1340 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ macro
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