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Searched refs:RADEON_TEX_0_ENABLE (Results 1 – 5 of 5) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_blit.c155 OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
179 OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
209 OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE |
/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_blit.c126 OUT_BATCH_REGVAL(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); in emit_tx_setup()
Dradeon_texstate.c1007 (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit; in radeon_validate_texture()
/external/mesa3d/src/mesa/drivers/dri/radeon/server/
Dradeon_reg.h1147 # define RADEON_TEX_0_ENABLE (1 << 4) macro
/external/mesa3d/src/mesa/drivers/dri/r200/server/
Dradeon_reg.h1147 # define RADEON_TEX_0_ENABLE (1 << 4) macro