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Searched refs:RAM (Results 1 – 25 of 179) sorted by relevance

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/external/arm-trusted-firmware/bl2u/
Dbl2u.ld.S17 RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE
35 } >RAM
40 } >RAM
44 } >RAM
54 } >RAM
73 } >RAM
82 DATA_SECTION >RAM
83 STACK_SECTION >RAM
84 BSS_SECTION >RAM
85 XLAT_TABLE_SECTION >RAM
[all …]
/external/arm-trusted-firmware/bl2/
Dbl2.ld.S15 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
33 } >RAM
38 } >RAM
42 } >RAM
52 } >RAM
71 } >RAM
80 DATA_SECTION >RAM
81 STACK_SECTION >RAM
82 BSS_SECTION >RAM
83 XLAT_TABLE_SECTION >RAM
[all …]
Dbl2_el3.ld.S17 RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE
19 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
24 #define ROM RAM
104 DATA_SECTION >RAM AT>ROM
108 RELA_SECTION >RAM
109 STACK_SECTION >RAM
110 BSS_SECTION >RAM
111 XLAT_TABLE_SECTION >RAM
131 } >RAM
/external/arm-trusted-firmware/bl32/sp_min/
Dsp_min.ld.S15 RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE
36 } >RAM
41 } >RAM
45 } >RAM
59 } >RAM
83 } >RAM
94 DATA_SECTION >RAM
100 STACK_SECTION >RAM
101 BSS_SECTION >RAM
102 XLAT_TABLE_SECTION >RAM
[all …]
/external/arm-trusted-firmware/bl32/tsp/
Dtsp.ld.S16 RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
34 } >RAM
44 } >RAM
64 } >RAM
73 DATA_SECTION >RAM
74 RELA_SECTION >RAM
80 STACK_SECTION >RAM
81 BSS_SECTION >RAM
82 XLAT_TABLE_SECTION >RAM
102 } >RAM
/external/arm-trusted-firmware/plat/marvell/armada/a8k/common/ble/
Dble.ld.S15 RAM (rwx): ORIGIN = BLE_BASE, LENGTH = BLE_LIMIT - BLE_BASE
29 } >RAM
41 } >RAM
47 } >RAM
53 } >RAM
64 . = ORIGIN(RAM) + LENGTH(RAM) - 1;
66 } >RAM
/external/arm-trusted-firmware/bl31/
Dbl31.ld.S16 RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE
20 #define NOBITS RAM
44 } >RAM
58 } >RAM
81 } >RAM
89 #define SPM_SHIM_EXCEPTIONS_VMA RAM
105 } >SPM_SHIM_EXCEPTIONS_VMA AT>RAM
117 DATA_SECTION >RAM
118 RELA_SECTION >RAM
/external/arm-trusted-firmware/plat/mediatek/mt6795/
Dbl31.ld.S16 RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_TZRAM_SIZE
31 } >RAM
51 } >RAM
62 DATA_SECTION >RAM
68 STACK_SECTION >RAM
69 BSS_SECTION >RAM
/external/arm-trusted-firmware/bl1/
Dbl1.ld.S24 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE
98 DATA_SECTION >RAM AT>ROM
102 STACK_SECTION >RAM
103 BSS_SECTION >RAM
104 XLAT_TABLE_SECTION >RAM
124 } >RAM
/external/tensorflow/tensorflow/lite/micro/tools/make/targets/stm32f4/
Dstm32f4.lds19 /* 256K of RAM and 2048K of FLASH. Source: */
22 RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K
27 _ld_stack_end_addr = ORIGIN(RAM) + LENGTH(RAM);
61 } >RAM AT> FLASH
72 } >RAM
80 } >RAM
/external/tensorflow/tensorflow/lite/micro/tools/make/targets/bluepill/
Dbluepill.lds20 * increased the flash size to 512K and RAM to 256K. This far exceeds the
37 RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K
42 _ld_stack_end_addr = ORIGIN(RAM) + LENGTH(RAM);
76 } >RAM AT> FLASH
87 } >RAM
95 } >RAM
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/
DSTM32L4A6RG_FLASH.ld8 ** 1024KByte FLASH, 320KByte RAM
35 _estack = 0x20050000; /* end of RAM */
36 /* Generate a link error if heap and stack don't fit into RAM */
43 RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 320K
133 /* Initialized data sections goes into RAM, load LMA copy after code */
143 } >RAM AT> FLASH
160 } >RAM
162 /* User_heap_stack section, used to check that there is enough RAM left */
171 } >RAM
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/
DSTM32L476RG_FLASH.ld8 ** 1024KByte FLASH, 128KByte RAM
35 _estack = 0x20018000; /* end of RAM */
36 /* Generate a link error if heap and stack don't fit into RAM */
43 RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
134 /* Initialized data sections goes into RAM, load LMA copy after code */
144 } >RAM AT> FLASH
178 } >RAM
180 /* User_heap_stack section, used to check that there is enough RAM left */
189 } >RAM
/external/llvm-project/lld/test/ELF/linkerscript/
Dat7.test7 RAM : ORIGIN = 0x20000000, LENGTH = 0x200
11 .text : { *(.text) } > RAM AT> RAM
12 .sec : { *(.sec) } > RAM
Dat8.test8 RAM : ORIGIN = 0x20000000, LENGTH = 0x200
13 .sec1 : { *(.sec1) } > RAM AT > FLASH
14 .sec2 : { *(.sec2) } > RAM AT > FLASH
15 .sec3 : { *(.sec3) } > RAM AT > FLASH
Dmemory.s4 ## Check simple RAM-only memory region.
12 # RUN: llvm-readelf -S %t1 | FileCheck --check-prefix=RAM %s
14 # RAM: [ 1] .text PROGBITS 0000000000008000 001000 000001
15 # RAM-NEXT: [ 2] .data PROGBITS 0000000000008001 001001 001000
17 ## Check RAM and ROM memory regions.
Dsection-include.test16 # RUN: echo ".data2 : { QUAD(0) } > RAM" > %t.dir/inc.script
25 RAM (rwx): ORIGIN = 0x2000, LENGTH = 0x100
30 .data : { *(.data*) } > RAM
32 .data3 : { QUAD(0) } > RAM
Dregion-alias.s13 ## .text to ROM, .data to RAM.
25 # RUN: llvm-objdump --section-headers %t2 | FileCheck %s --check-prefix=RAM
26 # RAM: .text 00000001 0000000000001000 TEXT
27 # RAM: .data 00000008 0000000000001001 DATA
Dlma-align.test26 RAM : ORIGIN = 0x11000, LENGTH = 1K
31 .data.rel.ro 0x11000 : { *(.data.rel.ro) } >RAM AT>ROM
33 .data . : ALIGN(16) { *(.data*) } >RAM AT>ROM
35 .bss . : ALIGN(64) { *(.bss*) } >RAM
Dat6.test8 RAM : ORIGIN = 0x20000000, LENGTH = 0x200
13 .sec1 : { *(.sec1) } > RAM
14 .sec2 : { *(.sec2) } > RAM AT > FLASH
Dat2.test11 RAM (aw) : ORIGIN = 0x7000, LENGTH = 0x100
22 .bar2 : { *(.bar2) } > AW AT > RAM
24 .bar4 : { *(.bar4) } > AW AT >RAM
/external/cpuinfo/test/dmesg/
Dzenfone-2.log7 [ 0.000000] e820: BIOS-provided physical RAM map:
50 [ 0.000000] total RAM covered: 4065M
51 [ 0.000000] gran_size: 64K chunk_size: 64K num_reg: 8 lose cover RAM: 3063M
52 [ 0.000000] gran_size: 64K chunk_size: 128K num_reg: 8 lose cover RAM: 3063M
53 [ 0.000000] gran_size: 64K chunk_size: 256K num_reg: 8 lose cover RAM: 3063M
54 [ 0.000000] gran_size: 64K chunk_size: 512K num_reg: 8 lose cover RAM: 3063M
55 [ 0.000000] gran_size: 64K chunk_size: 1M num_reg: 8 lose cover RAM: 3063M
56 [ 0.000000] gran_size: 64K chunk_size: 2M num_reg: 8 lose cover RAM: 3063M
57 [ 0.000000] gran_size: 64K chunk_size: 4M num_reg: 8 lose cover RAM: 3831M
58 [ 0.000000] gran_size: 64K chunk_size: 8M num_reg: 8 lose cover RAM: 3983M
[all …]
/external/pigweed/pw_persistent_ram/
Ddocs.rst7 persistent RAM. By persistent RAM we are referring to memory which is not
24 Persistent RAM Placement
26 Persistent RAM is typically provided through specially carved out linker script
70 Persistent RAM Lifecycle Management
72 In order for persistent RAM containers to be as useful as possible, any
73 invalidation of persistent RAM and the containers therein should be executed
75 are initialized in RAM.
77 The preferred way to clear Persistent RAM is to simply zero entire persistent
78 RAM sections and/or memory regions. Pigweed's persistents containers have picked
87 1. Do not instantiate regular types/objects in persistent RAM, ensure integrity
[all …]
/external/pigweed/pw_boot_armv7m/
Dbasic_armv7m.ld18 * that have on-board memory-mapped RAM and FLASH. For more complex projects and
80 RAM(rwx) : \
149 } >RAM AT> FLASH
159 } >RAM
167 } >RAM
174 HIDDEN(_stack_size = ORIGIN(RAM) + LENGTH(RAM) - .);
178 "Error: Not enough RAM for desired minimum stack size.");
181 } >RAM
194 /* Region of .static_init_ram in RAM. */
/external/arm-trusted-firmware/lib/romlib/
Dromlib.ld.S12 RAM (rwx): ORIGIN = ROMLIB_RW_BASE, LENGTH = ROMLIB_RW_END - ROMLIB_RW_BASE
34 } >RAM AT>ROM
42 } >RAM

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