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Searched refs:RCId (Results 1 – 19 of 19) sorted by relevance

/external/llvm/lib/CodeGen/GlobalISel/
DRegisterBank.cpp28 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) { in verify() local
29 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
40 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
96 for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) { in print() local
97 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
DRegisterBankInfo.cpp67 void RegisterBankInfo::addRegBankCoverage(unsigned ID, unsigned RCId, in addRegBankCoverage() argument
78 else if (RB.covers(*TRI.getRegClass(RCId))) in addRegBankCoverage()
86 WorkList.push_back(RCId); in addRegBankCoverage()
87 Covered.set(RCId); in addRegBankCoverage()
91 unsigned RCId = WorkList.pop_back_val(); in addRegBankCoverage() local
93 const TargetRegisterClass &CurRC = *TRI.getRegClass(RCId); in addRegBankCoverage()
149 if (SuperRCId == RCId) { in addRegBankCoverage()
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DRegisterBank.cpp33 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) { in verify() local
34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
103 for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) { in print() local
104 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DRegisterBank.cpp33 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) { in verify() local
34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
103 for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) { in print() local
104 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DResourcePriorityQueue.h112 int rawRegPressureDelta (SUnit *SU, unsigned RCId);
130 unsigned numberRCValPredInSU (SUnit *SU, unsigned RCId);
131 unsigned numberRCValSuccInSU (SUnit *SU, unsigned RCId);
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp71 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { in numberRCValPredInSU() argument
99 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
109 unsigned RCId) { in numberRCValSuccInSU() argument
137 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
323 int ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) { in rawRegPressureDelta() argument
334 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
335 RegBalance += numberRCValSuccInSU(SU, RCId); in rawRegPressureDelta()
345 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
346 RegBalance -= numberRCValPredInSU(SU, RCId); in rawRegPressureDelta()
DScheduleDAGRRList.cpp2101 unsigned RCId, Cost; in HighRegPressure() local
2102 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF); in HighRegPressure()
2104 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) in HighRegPressure()
2122 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in MayReduceRegPressure() local
2123 if (RegPressure[RCId] >= RegLimit[RCId]) in MayReduceRegPressure()
2153 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in RegPressureDiff() local
2154 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2168 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in RegPressureDiff() local
2169 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2213 unsigned RCId, Cost; in scheduledNode() local
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp67 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { in numberRCValPredInSU() argument
95 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
105 unsigned RCId) { in numberRCValSuccInSU() argument
133 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
319 int ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) { in rawRegPressureDelta() argument
330 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
331 RegBalance += numberRCValSuccInSU(SU, RCId); in rawRegPressureDelta()
341 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
342 RegBalance -= numberRCValPredInSU(SU, RCId); in rawRegPressureDelta()
DScheduleDAGRRList.cpp2098 unsigned RCId, Cost; in HighRegPressure() local
2099 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF); in HighRegPressure()
2101 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) in HighRegPressure()
2119 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in MayReduceRegPressure() local
2120 if (RegPressure[RCId] >= RegLimit[RCId]) in MayReduceRegPressure()
2150 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in RegPressureDiff() local
2151 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2165 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in RegPressureDiff() local
2166 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2210 unsigned RCId, Cost; in scheduledNode() local
[all …]
/external/llvm/include/llvm/CodeGen/
DResourcePriorityQueue.h113 int rawRegPressureDelta (SUnit *SU, unsigned RCId);
131 unsigned numberRCValPredInSU (SUnit *SU, unsigned RCId);
132 unsigned numberRCValSuccInSU (SUnit *SU, unsigned RCId);
/external/llvm-project/llvm/include/llvm/CodeGen/
DResourcePriorityQueue.h111 int rawRegPressureDelta (SUnit *SU, unsigned RCId);
129 unsigned numberRCValPredInSU (SUnit *SU, unsigned RCId);
130 unsigned numberRCValSuccInSU (SUnit *SU, unsigned RCId);
/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp70 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { in numberRCValPredInSU() argument
98 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
108 unsigned RCId) { in numberRCValSuccInSU() argument
136 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
326 int ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) { in rawRegPressureDelta() argument
337 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
338 RegBalance += numberRCValSuccInSU(SU, RCId); in rawRegPressureDelta()
348 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
349 RegBalance -= numberRCValPredInSU(SU, RCId); in rawRegPressureDelta()
DScheduleDAGRRList.cpp1957 unsigned RCId, Cost; in HighRegPressure() local
1958 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF); in HighRegPressure()
1960 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) in HighRegPressure()
1978 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in MayReduceRegPressure() local
1979 if (RegPressure[RCId] >= RegLimit[RCId]) in MayReduceRegPressure()
2009 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in RegPressureDiff() local
2010 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2024 unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); in RegPressureDiff() local
2025 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2069 unsigned RCId, Cost; in scheduledNode() local
[all …]
/external/llvm/lib/Target/NVPTX/InstPrinter/
DNVPTXInstPrinter.cpp38 unsigned RCId = (RegNo >> 28); in printRegName() local
39 switch (RCId) { in printRegName()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/MCTargetDesc/
DNVPTXInstPrinter.cpp37 unsigned RCId = (RegNo >> 28); in printRegName() local
38 switch (RCId) { in printRegName()
/external/llvm-project/llvm/lib/Target/NVPTX/MCTargetDesc/
DNVPTXInstPrinter.cpp37 unsigned RCId = (RegNo >> 28); in printRegName() local
38 switch (RCId) { in printRegName()
/external/llvm/include/llvm/CodeGen/GlobalISel/
DRegisterBankInfo.h345 void addRegBankCoverage(unsigned ID, unsigned RCId,
/external/clang/lib/Sema/
DSemaExprObjC.cpp3856 IdentifierInfo *RCId = ObjCBAttr->getRelatedClass(); in checkObjCBridgeRelatedComponents() local
3859 if (!RCId) in checkObjCBridgeRelatedComponents()
3863 LookupResult R(*this, DeclarationName(RCId), SourceLocation(), in checkObjCBridgeRelatedComponents()
3867 Diag(Loc, diag::err_objc_bridged_related_invalid_class) << RCId in checkObjCBridgeRelatedComponents()
3878 Diag(Loc, diag::err_objc_bridged_related_invalid_class_name) << RCId in checkObjCBridgeRelatedComponents()
/external/llvm-project/clang/lib/Sema/
DSemaExprObjC.cpp4236 IdentifierInfo *RCId = ObjCBAttr->getRelatedClass(); in checkObjCBridgeRelatedComponents() local
4239 if (!RCId) in checkObjCBridgeRelatedComponents()
4243 LookupResult R(*this, DeclarationName(RCId), SourceLocation(), in checkObjCBridgeRelatedComponents()
4247 Diag(Loc, diag::err_objc_bridged_related_invalid_class) << RCId in checkObjCBridgeRelatedComponents()
4258 Diag(Loc, diag::err_objc_bridged_related_invalid_class_name) << RCId in checkObjCBridgeRelatedComponents()