| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | rcp-pattern.ll | 8 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
9 ; GCN: buffer_store_dword [[RCP]]
20 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
21 ; GCN: buffer_store_dword [[RCP]]
32 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
33 ; GCN: buffer_store_dword [[RCP]]
44 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
45 ; GCN: buffer_store_dword [[RCP]]
56 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
57 ; GCN: buffer_store_dword [[RCP]]
[all …]
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| D | fdiv32-to-rcp-folding.ll | 11 ; GCN-DENORM: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[PRESCALED]]
12 ; GCN-DENORM: v_mul_f32_e32 [[OUT:v[0-9]+]], [[SCALE]], [[RCP]]
31 ; GCN-DENORM: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[PRESCALED]]
32 ; GCN-DENORM: v_mul_f32_e32 [[OUT:v[0-9]+]], [[SCALE]], [[RCP]]
51 ; GCN-DENORM: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[PRESCALED]]
52 ; GCN-DENORM: v_mul_f32_e32 [[OUT:v[0-9]+]], [[SCALE]], [[RCP]]
72 ; GCN-DENORM: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[PRESCALED]]
73 ; GCN-DENORM: v_mul_f32_e32 [[OUT:v[0-9]+]], [[SCALE]], [[RCP]]
336 ; GCN-FLUSH: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[PRESCALED]]
337 ; GCN-FLUSH: v_mul_f32_e32 [[OUT:v[0-9]+]], [[SCALE]], [[RCP]]
[all …]
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| D | rsq.ll | 53 ; SI-UNSAFE-DAG: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[MUL]]
54 ; SI-UNSAFE-DAG: v_mul_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[RCP]]
99 ; SI-UNSAFE: v_rcp_f64_e64 [[RCP:v\[[0-9]+:[0-9]+\]]], -[[SQRT]]
100 ; SI-UNSAFE: buffer_store_dwordx2 [[RCP]]
131 ; SI-UNSAFE: v_rcp_f64_e64 [[RCP:v\[[0-9]+:[0-9]+\]]], -[[SQRT]]
132 ; SI-UNSAFE: buffer_store_dwordx2 [[RCP]]
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| D | select-fabs-fneg-extract-legacy.ll | 10 ; GCN: v_rcp_legacy_f32_e32 [[RCP:v[0-9]+]], [[X]]
11 ; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], -2.0, [[RCP]], vcc
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| D | fdiv.ll | 102 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
103 ; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
119 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
120 ; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
134 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
135 ; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
149 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
150 ; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
|
| D | fdiv.f16.ll | 190 ; GFX8_9_10: v_rcp_f16_e32 [[RCP:v[0-9]+]], [[RHS]]
191 ; GFX8_9_10: v_mul_f16_e32 [[RESULT:v[0-9]+]], [[LHS]], [[RCP]]
212 ; GFX8_9_10: v_rcp_f16_e32 [[RCP:v[0-9]+]], [[RHS]]
213 ; GFX8_9_10: v_mul_f16_e32 [[RESULT:v[0-9]+]], [[LHS]], [[RCP]]
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| /external/mesa3d/src/gallium/drivers/r300/compiler/tests/ |
| D | omod_two_writers.test | 1 RCP temp[0].x, const[1].x___;
2 RCP temp[0].y, const[1]._y__;
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | udivrem.ll | 30 ; SI: v_rcp_iflag_f32_e32 [[RCP:v[0-9]+]]
31 ; SI-DAG: v_mul_hi_u32 [[RCP_HI:v[0-9]+]], [[RCP]]
32 ; SI-DAG: v_mul_lo_i32 [[RCP_LO:v[0-9]+]], [[RCP]]
35 ; SI: v_mul_hi_u32 [[E:v[0-9]+]], {{v[0-9]+}}, [[RCP]]
36 ; SI-DAG: v_add_i32_e32 [[RCP_A_E:v[0-9]+]], vcc, [[E]], [[RCP]]
37 ; SI-DAG: v_subrev_i32_e32 [[RCP_S_E:v[0-9]+]], vcc, [[E]], [[RCP]]
|
| /external/mesa3d/src/gallium/tests/graw/fragment-shader/ |
| D | frag-cb-1d.sh | 10 RCP TEMP[1], CONST[0][3].xxxx
|
| D | frag-rcp.sh | 12 RCP TEMP[0].x, TEMP[0].xxxx
|
| /external/mesa3d/src/gallium/tests/graw/vertex-shader/ |
| D | vert-cb-1d.sh | 13 RCP TEMP[1], CONST[0][3].xxxx
|
| D | vert-rcp.sh | 14 RCP TEMP[0].x, TEMP[0].xxxx
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCodeGenPrepare.cpp | 688 Value *RCP = Builder.CreateFDiv(ConstantFP::get(F32Ty, 1.0), FB); in expandDivRem24() local
689 Value *FQM = Builder.CreateFMul(FA, RCP); in expandDivRem24()
801 Value *RCP = Builder.CreateFPToUI(RCP_SCALE, I32Ty); in expandDivRem32() local
805 std::tie(RCP_LO, RCP_HI) = getMul64(Builder, RCP, Den); in expandDivRem32()
816 Value *E = getMulHu(Builder, ABS_RCP_LO, RCP); in expandDivRem32()
819 Value *RCP_A_E = Builder.CreateAdd(RCP, E); in expandDivRem32()
822 Value *RCP_S_E = Builder.CreateSub(RCP, E); in expandDivRem32()
|
| D | AMDGPULegalizerInfo.cpp | 1985 auto RCP = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {ResTy}, false) in legalizeFastUnsafeFDIV() local
1988 B.buildFMul(Res, LHS, RCP, Flags); in legalizeFastUnsafeFDIV()
2013 auto RCP = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S32}, false) in legalizeFDIV16() local
2017 auto QUOT = B.buildFMul(S32, LHSExt, RCP, Flags); in legalizeFDIV16()
2234 auto RCP = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S32}, false) in legalizeFDIVFastIntrin() local
2238 auto Mul1 = B.buildFMul(S32, LHS, RCP, Flags); in legalizeFDIVFastIntrin()
|
| D | AMDGPUISelLowering.cpp | 527 case AMDGPUISD::RCP: in fnegFoldsIntoOp()
1579 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb)); in LowerDIVREM24()
1685 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1); in LowerUDIVREM64()
1869 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den); in LowerUDIVREM() local
1872 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den); in LowerUDIVREM()
1875 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den); in LowerUDIVREM()
1887 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP); in LowerUDIVREM()
1890 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E); in LowerUDIVREM()
1893 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E); in LowerUDIVREM()
3811 case AMDGPUISD::RCP: in performFNegCombine()
[all …]
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| /external/virglrenderer/src/gallium/auxiliary/tgsi/ |
| D | tgsi_opcode_tmp.h | 62 OP11(RCP)
|
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_opcode_tmp.h | 42 OP11(RCP)
|
| D | tgsi_info_opcodes.h | 4 OPCODE(1, 1, REPL, RCP)
|
| /external/mesa3d/src/mesa/program/ |
| D | program_lexer.l | 221 RCP{sat} { return_opcode( 1, SCALAR_OP, RCP, 3); }
|
| /external/mesa3d/docs/relnotes/ |
| D | 18.2.2.rst | 57 - st/nine: Clamp RCP when 0*inf!=0
|
| D | 8.0.4.rst | 101 - nv50: handle NEG,ABS modifiers for short RCP encoding
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.h | 255 RCP, enumerator
|
| D | AMDGPUISelLowering.cpp | 1284 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb)); in LowerDIVREM24()
1433 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den); in LowerUDIVREM() local
1436 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den); in LowerUDIVREM()
1439 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den); in LowerUDIVREM()
1451 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP); in LowerUDIVREM()
1454 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E); in LowerUDIVREM()
1457 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E); in LowerUDIVREM()
2826 NODE_NAME_CASE(RCP) in getTargetNodeName()
2908 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand); in getRecipEstimate()
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| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_compiler_nir_emit.c | 68 OP(ffract, FRC, X_X_0), OP(frcp, RCP, X_X_0), OP(frsq, RSQ, X_X_0),
|
| D | etnaviv_disasm.c | 475 OPC(RCP),
|