Searched refs:RCR (Results 1 – 25 of 31) sorted by relevance
12
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86FlagsCopyLowering.cpp | 162 RCR, enumerator
217 LLVM_EXPAND_INSTR_SIZES(RCR, rCL) in getMnemonicFromOpcode()
218 LLVM_EXPAND_INSTR_SIZES(RCR, r1) in getMnemonicFromOpcode()
219 LLVM_EXPAND_INSTR_SIZES(RCR, ri) in getMnemonicFromOpcode()
220 return FlagArithMnemonic::RCR; in getMnemonicFromOpcode()
807 case FlagArithMnemonic::RCR: in rewriteArithmetic()
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| D | X86SchedBroadwell.td | 809 "RCR(8|16|32|64)r(1|i)")>;
1171 "RCR(8|16|32|64)m(1|i)")>;
1305 "RCR(16|32|64)rCL")>;
1412 def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
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| D | X86SchedSandyBridge.td | 678 "RCR(8|16|32|64)r1")>;
722 "RCR(8|16|32|64)r(i|CL)")>;
1058 "RCR(8|16|32|64)m")>;
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| D | X86SchedHaswell.td | 1280 "RCR(8|16|32|64)r(1|i)")>;
1303 "RCR(8|16|32|64)m(1|i)")>;
1575 "RCR(16|32|64)rCL")>;
1603 def: InstRW<[HWWriteResGroup135], (instregex "RCR(8|16|32|64)mCL")>;
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| D | X86SchedSkylakeClient.td | 832 "RCR(8|16|32|64)r(1|i)")>;
1251 "RCR(8|16|32|64)m(1|i)")>;
1427 "RCR(16|32|64)rCL")>;
1547 def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;
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| D | X86SchedSkylakeServer.td | 901 "RCR(8|16|32|64)r(1|i)")>;
1610 "RCR(8|16|32|64)m(1|i)")>;
1951 "RCR(16|32|64)rCL")>;
2155 def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>;
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| D | X86ScheduleAtom.td | 507 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
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| D | X86ScheduleZnver2.td | 765 // RCR RCL.
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| D | X86ScheduleZnver1.td | 756 // RCR RCL.
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FlagsCopyLowering.cpp | 166 RCR, enumerator
220 LLVM_EXPAND_INSTR_SIZES(RCR, rCL) in getMnemonicFromOpcode()
221 LLVM_EXPAND_INSTR_SIZES(RCR, r1) in getMnemonicFromOpcode()
222 LLVM_EXPAND_INSTR_SIZES(RCR, ri) in getMnemonicFromOpcode()
223 return FlagArithMnemonic::RCR; in getMnemonicFromOpcode()
822 case FlagArithMnemonic::RCR: in rewriteArithmetic()
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| D | X86SchedBroadwell.td | 806 "RCR(8|16|32|64)r(1|i)")>;
1168 "RCR(8|16|32|64)m(1|i)")>;
1302 "RCR(16|32|64)rCL")>;
1409 def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
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| D | X86SchedSandyBridge.td | 675 "RCR(8|16|32|64)r1")>;
719 "RCR(8|16|32|64)r(i|CL)")>;
1055 "RCR(8|16|32|64)m")>;
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| D | X86SchedSkylakeClient.td | 829 "RCR(8|16|32|64)r(1|i)")>;
1248 "RCR(8|16|32|64)m(1|i)")>;
1424 "RCR(16|32|64)rCL")>;
1544 def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;
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| D | X86SchedHaswell.td | 1277 "RCR(8|16|32|64)r(1|i)")>;
1300 "RCR(8|16|32|64)m(1|i)")>;
1572 "RCR(16|32|64)rCL")>;
1600 def: InstRW<[HWWriteResGroup135], (instregex "RCR(8|16|32|64)mCL")>;
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| D | X86SchedSkylakeServer.td | 890 "RCR(8|16|32|64)r(1|i)")>;
1600 "RCR(8|16|32|64)m(1|i)")>;
1924 "RCR(16|32|64)rCL")>;
2128 def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>;
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| D | X86ScheduleAtom.td | 504 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
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| D | X86ScheduleZnver2.td | 753 // RCR RCL.
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| D | X86ScheduleZnver1.td | 753 // RCR RCL.
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| D | X86InstrInfo.td | 3514 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1890 auto *RCR = MRI.getRegClass(R.Reg); in optimizeSpillSlots() local
1892 return RCR; in optimizeSpillSlots()
1893 unsigned PR = *RCR->begin(); in optimizeSpillSlots()
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| /external/icu/icu4c/source/data/locales/ |
| D | ga.txt | 828 "RCR",
836 "RCR",
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| /external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/ |
| D | stm32l4xx_hal_tim.c | 4780 TIMx->RCR = Structure->RepetitionCounter; in TIM_Base_SetConfig()
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| /external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/ |
| D | stm32l4xx_hal_tim.c | 4780 TIMx->RCR = Structure->RepetitionCounter; in TIM_Base_SetConfig()
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| /external/llvm/lib/Target/X86/ |
| D | X86SchedHaswell.td | 766 // RCR RCL.
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| D | X86InstrInfo.td | 3042 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
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