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Searched refs:RD2 (Results 1 – 14 of 14) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/Mips/msa/
Di5-c.ll27 ; CHECK: ceqi.b [[RD2:\$w[0-9]]], [[RS]], -14
28 ; CHECK: st.b [[RD2]]
51 ; CHECK: ceqi.h [[RD2:\$w[0-9]]], [[RS]], -14
52 ; CHECK: st.h [[RD2]]
75 ; CHECK: ceqi.w [[RD2:\$w[0-9]]], [[RS]], -14
76 ; CHECK: st.w [[RD2]]
99 ; CHECK: ceqi.d [[RD2:\$w[0-9]]], [[RS]], -14
100 ; CHECK: st.d [[RD2]]
123 ; CHECK: clei_s.b [[RD2:\$w[0-9]]], [[RS]], -14
124 ; CHECK: st.b [[RD2]]
[all …]
Di5-m.ll27 ; CHECK: maxi_s.b [[RD2:\$w[0-9]]], [[RS]], -14
28 ; CHECK: st.b [[RD2]]
51 ; CHECK: maxi_s.h [[RD2:\$w[0-9]]], [[RS]], -14
52 ; CHECK: st.h [[RD2]]
75 ; CHECK: maxi_s.w [[RD2:\$w[0-9]]], [[RS]], -14
76 ; CHECK: st.w [[RD2]]
99 ; CHECK: maxi_s.d [[RD2:\$w[0-9]]], [[RS]], -14
100 ; CHECK: st.d [[RD2]]
199 ; CHECK: mini_s.b [[RD2:\$w[0-9]]], [[RS]], -14
200 ; CHECK: st.b [[RD2]]
[all …]
Delm_copy.ll101 ; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3]
106 ; MIPS32-DAG: sw [[RD2]], 4([[RES]])
199 ; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3]
204 ; MIPS32-DAG: sw [[RD2]], 4([[RES]])
/external/llvm/test/Transforms/BBVectorize/
Dreq-depth.ll3 …torize-req-chain-depth 2 -bb-vectorize-ignore-target-info -S | FileCheck %s -check-prefix=CHECK-RD2
13 ; CHECK-RD2-LABEL: @test1(
15 ; CHECK-RD2: <2 x double>
/external/llvm/test/CodeGen/Mips/msa/
Delm_copy.ll101 ; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3]
106 ; MIPS32-DAG: sw [[RD2]], 4([[RES]])
199 ; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3]
204 ; MIPS32-DAG: sw [[RD2]], 4([[RES]])
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dfunnel-shift.ll122 ; CHECK: r[[RD2:[0-9]+]]:[[RD3:[0-9]+]] = lsr(r[[RD0]]:[[RD1]],r1)
/external/clang/lib/Sema/
DSemaChecking.cpp10560 RecordDecl *RD2) { in isLayoutCompatibleStruct() argument
10565 const CXXRecordDecl *D2CXX = cast<CXXRecordDecl>(RD2); in isLayoutCompatibleStruct()
10580 } else if (const CXXRecordDecl *D2CXX = dyn_cast<CXXRecordDecl>(RD2)) { in isLayoutCompatibleStruct()
10587 RecordDecl::field_iterator Field2 = RD2->field_begin(), in isLayoutCompatibleStruct()
10588 Field2End = RD2->field_end(), in isLayoutCompatibleStruct()
10605 RecordDecl *RD2) { in isLayoutCompatibleUnion() argument
10607 for (auto *Field2 : RD2->fields()) in isLayoutCompatibleUnion()
10630 bool isLayoutCompatible(ASTContext &C, RecordDecl *RD1, RecordDecl *RD2) { in isLayoutCompatible() argument
10631 if (RD1->isUnion() != RD2->isUnion()) in isLayoutCompatible()
10635 return isLayoutCompatibleUnion(C, RD1, RD2); in isLayoutCompatible()
[all …]
/external/llvm-project/clang/lib/Sema/
DSemaChecking.cpp15266 RecordDecl *RD2) { in isLayoutCompatibleStruct() argument
15271 const CXXRecordDecl *D2CXX = cast<CXXRecordDecl>(RD2); in isLayoutCompatibleStruct()
15286 } else if (const CXXRecordDecl *D2CXX = dyn_cast<CXXRecordDecl>(RD2)) { in isLayoutCompatibleStruct()
15293 RecordDecl::field_iterator Field2 = RD2->field_begin(), in isLayoutCompatibleStruct()
15294 Field2End = RD2->field_end(), in isLayoutCompatibleStruct()
15310 RecordDecl *RD2) { in isLayoutCompatibleUnion() argument
15312 for (auto *Field2 : RD2->fields()) in isLayoutCompatibleUnion()
15336 RecordDecl *RD2) { in isLayoutCompatible() argument
15337 if (RD1->isUnion() != RD2->isUnion()) in isLayoutCompatible()
15341 return isLayoutCompatibleUnion(C, RD1, RD2); in isLayoutCompatible()
[all …]
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp3029 unsigned RD2 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo() local
3030 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2) in emitMSACBranchPseudo()
3038 .addReg(RD2) in emitMSACBranchPseudo()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp3142 Register RD2 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo() local
3143 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2) in emitMSACBranchPseudo()
3151 .addReg(RD2) in emitMSACBranchPseudo()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp3143 Register RD2 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo() local
3144 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2) in emitMSACBranchPseudo()
3152 .addReg(RD2) in emitMSACBranchPseudo()
/external/cldr/tools/java/org/unicode/cldr/util/data/external/
D2013-1_UNLOCODE_CodeListPart2.csv14263 ,"IT","RD2","Rocca de' Giorgi","Rocca de' Giorgi","PV","--3-----","RL","1207",,"4457N 00915E",
D2013-1_UNLOCODE_CodeListPart1.csv23150 ,"DE","RD2","Reinhardshagen","Reinhardshagen","HE","--3--6--","RL","1207",,"5129N 00936E",
40273 "+","FR","RD2","Radon","Radon","61","--3-----","RL","1301",,"4831N 00006E",
D2013-1_UNLOCODE_CodeListPart3.csv22935 ,"US","RD2","Reeder","Reeder","ND","-23--6--","RL","0607",,"4606N 10257W",