Searched refs:REG_Z (Results 1 – 3 of 3) sorted by relevance
| /external/igt-gpu-tools/lib/ |
| D | i915_3d.h | 302 #define REG_Z(reg) (((reg) >> Z_CHANNEL_SHIFT) & REG_CHANNEL_MASK) macro
412 i915_get_hardware_channel_val(REG_Z(operand0), \
427 OUT_BATCH(i915_get_hardware_channel_val(REG_Z(operand1), \
442 i915_get_hardware_channel_val(REG_Z(operand2), \
465 i915_get_hardware_channel_val(REG_Z(operand0), \
480 OUT_BATCH(i915_get_hardware_channel_val(REG_Z(operand1), \
495 i915_get_hardware_channel_val(REG_Z(operand2), \
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | ds_read2_superreg.ll | 40 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_Z:[0-9]+]]:[[REG_W:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset…
41 ; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_X]], v[[REG_Z]]
66 ; CI-DAG: ds_read_b32 v[[REG_Z:[0-9]+]], v{{[0-9]+}} offset:8{{$}}
67 ; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_X]], v[[REG_Z]]
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | ds_read2_superreg.ll | 40 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_Z:[0-9]+]]:[[REG_W:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset…
41 ; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_Z]], v[[REG_X]]
66 ; CI-DAG: ds_read_b32 v[[REG_Z:[0-9]+]], v{{[0-9]+}} offset:8{{$}}
67 ; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_Z]], v[[REG_X]]
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