Home
last modified time | relevance | path

Searched refs:RISCV (Results 1 – 25 of 150) sorted by relevance

123456

/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVRegisterInfo.cpp30 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
31 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
32 static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive");
33 static_assert(RISCV::F31_H == RISCV::F0_H + 31,
35 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
36 static_assert(RISCV::F31_F == RISCV::F0_F + 31,
38 static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
39 static_assert(RISCV::F31_D == RISCV::F0_D + 31,
41 static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
42 static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
[all …]
DRISCVInstrInfo.cpp36 : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP), in RISCVInstrInfo()
44 case RISCV::LB: in isLoadFromStackSlot()
45 case RISCV::LBU: in isLoadFromStackSlot()
46 case RISCV::LH: in isLoadFromStackSlot()
47 case RISCV::LHU: in isLoadFromStackSlot()
48 case RISCV::FLH: in isLoadFromStackSlot()
49 case RISCV::LW: in isLoadFromStackSlot()
50 case RISCV::FLW: in isLoadFromStackSlot()
51 case RISCV::LWU: in isLoadFromStackSlot()
52 case RISCV::LD: in isLoadFromStackSlot()
[all …]
DRISCVExpandAtomicPseudoInsts.cpp93 case RISCV::PseudoAtomicLoadNand32: in expandMI()
96 case RISCV::PseudoAtomicLoadNand64: in expandMI()
99 case RISCV::PseudoMaskedAtomicSwap32: in expandMI()
102 case RISCV::PseudoMaskedAtomicLoadAdd32: in expandMI()
104 case RISCV::PseudoMaskedAtomicLoadSub32: in expandMI()
106 case RISCV::PseudoMaskedAtomicLoadNand32: in expandMI()
109 case RISCV::PseudoMaskedAtomicLoadMax32: in expandMI()
112 case RISCV::PseudoMaskedAtomicLoadMin32: in expandMI()
115 case RISCV::PseudoMaskedAtomicLoadUMax32: in expandMI()
118 case RISCV::PseudoMaskedAtomicLoadUMin32: in expandMI()
[all …]
DRISCVISelLowering.cpp83 addRegisterClass(XLenVT, &RISCV::GPRRegClass); in RISCVTargetLowering()
86 addRegisterClass(MVT::f16, &RISCV::FPR16RegClass); in RISCVTargetLowering()
88 addRegisterClass(MVT::f32, &RISCV::FPR32RegClass); in RISCVTargetLowering()
90 addRegisterClass(MVT::f64, &RISCV::FPR64RegClass); in RISCVTargetLowering()
93 addRegisterClass(RISCVVMVTs::vbool64_t, &RISCV::VRRegClass); in RISCVTargetLowering()
94 addRegisterClass(RISCVVMVTs::vbool32_t, &RISCV::VRRegClass); in RISCVTargetLowering()
95 addRegisterClass(RISCVVMVTs::vbool16_t, &RISCV::VRRegClass); in RISCVTargetLowering()
96 addRegisterClass(RISCVVMVTs::vbool8_t, &RISCV::VRRegClass); in RISCVTargetLowering()
97 addRegisterClass(RISCVVMVTs::vbool4_t, &RISCV::VRRegClass); in RISCVTargetLowering()
98 addRegisterClass(RISCVVMVTs::vbool2_t, &RISCV::VRRegClass); in RISCVTargetLowering()
[all …]
DRISCVMergeBaseOffset.cpp82 if (HiLUI.getOpcode() != RISCV::LUI || in INITIALIZE_PASS()
90 if (LoADDI->getOpcode() != RISCV::ADDI || in INITIALIZE_PASS()
137 assert((TailAdd.getOpcode() == RISCV::ADD) && "Expected ADD instruction!"); in matchLargeOffset()
147 if (OffsetTail.getOpcode() == RISCV::ADDI) { in matchLargeOffset()
157 if (OffsetLui.getOpcode() != RISCV::LUI || in matchLargeOffset()
168 } else if (OffsetTail.getOpcode() == RISCV::LUI) { in matchLargeOffset()
190 case RISCV::ADDI: { in detectAndFoldOffset()
197 case RISCV::ADD: { in detectAndFoldOffset()
212 case RISCV::LB: in detectAndFoldOffset()
213 case RISCV::LH: in detectAndFoldOffset()
[all …]
DRISCVFrameLowering.cpp62 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in emitSCSPrologue()
67 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW)) in emitSCSPrologue()
71 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI)) in emitSCSPrologue()
110 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in emitSCSEpilogue()
115 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW)) in emitSCSEpilogue()
119 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI)) in emitSCSEpilogue()
136 Register MaxReg = RISCV::NoRegister; in getLibCallID()
143 if (MaxReg == RISCV::NoRegister) in getLibCallID()
149 case /*s11*/ RISCV::X27: return 12; in getLibCallID()
150 case /*s10*/ RISCV::X26: return 11; in getLibCallID()
[all …]
DRISCVISelDAGToDAG.cpp36 SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT); in selectImm()
39 if (Inst.Opc == RISCV::LUI) in selectImm()
40 Result = CurDAG->getMachineNode(RISCV::LUI, DL, XLenVT, SDImm); in selectImm()
92 auto *NodeAddi0 = CurDAG->getMachineNode(RISCV::ADDI, DL, VT, in Select()
94 auto *NodeAddi1 = CurDAG->getMachineNode(RISCV::ADDI, DL, VT, in Select()
105 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, RISCV::X0, XLenVT); in Select()
120 ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ADDI, DL, VT, TFI, Imm)); in Select()
137 CurDAG->SelectNodeTo(Node, RISCV::SRLIW, XLenVT, Op0->getOperand(0), in Select()
391 case RISCV::LB: in doPeepholeLoadStoreADDI()
392 case RISCV::LH: in doPeepholeLoadStoreADDI()
[all …]
DRISCVExpandPseudoInsts.cpp95 case RISCV::PseudoLLA: in expandMI()
97 case RISCV::PseudoLA: in expandMI()
99 case RISCV::PseudoLA_TLS_IE: in expandMI()
101 case RISCV::PseudoLA_TLS_GD: in expandMI()
103 case RISCV::PseudoVSETVLI: in expandMI()
129 BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg) in expandAuipcInstPair()
155 RISCV::ADDI); in expandLoadLocalAddress()
167 SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW; in expandLoadAddress()
170 SecondOpcode = RISCV::ADDI; in expandLoadAddress()
182 unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW; in expandLoadTLSIEAddress()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/MCTargetDesc/
DRISCVAsmBackend.cpp42 case RISCV::fixup_riscv_got_hi20: in shouldForceRelocation()
43 case RISCV::fixup_riscv_tls_got_hi20: in shouldForceRelocation()
44 case RISCV::fixup_riscv_tls_gd_hi20: in shouldForceRelocation()
48 return STI.getFeatureBits()[RISCV::FeatureRelax] || ForceRelocs; in shouldForceRelocation()
68 case RISCV::fixup_riscv_rvc_branch: in fixupNeedsRelaxationAdvanced()
72 case RISCV::fixup_riscv_rvc_jump: in fixupNeedsRelaxationAdvanced()
86 case RISCV::C_BEQZ: in relaxInstruction()
88 Res.setOpcode(RISCV::BEQ); in relaxInstruction()
90 Res.addOperand(MCOperand::createReg(RISCV::X0)); in relaxInstruction()
93 case RISCV::C_BNEZ: in relaxInstruction()
[all …]
DRISCVELFObjectWriter.cpp63 case RISCV::fixup_riscv_pcrel_hi20: in getRelocType()
65 case RISCV::fixup_riscv_pcrel_lo12_i: in getRelocType()
67 case RISCV::fixup_riscv_pcrel_lo12_s: in getRelocType()
69 case RISCV::fixup_riscv_got_hi20: in getRelocType()
71 case RISCV::fixup_riscv_tls_got_hi20: in getRelocType()
73 case RISCV::fixup_riscv_tls_gd_hi20: in getRelocType()
75 case RISCV::fixup_riscv_jal: in getRelocType()
77 case RISCV::fixup_riscv_branch: in getRelocType()
79 case RISCV::fixup_riscv_rvc_jump: in getRelocType()
81 case RISCV::fixup_riscv_rvc_branch: in getRelocType()
[all …]
DRISCVMCCodeEmitter.cpp105 if (MI.getOpcode() == RISCV::PseudoTAIL) { in expandFunctionCall()
107 Ra = RISCV::X6; in expandFunctionCall()
108 } else if (MI.getOpcode() == RISCV::PseudoCALLReg) { in expandFunctionCall()
113 Ra = RISCV::X1; in expandFunctionCall()
122 TmpInst = MCInstBuilder(RISCV::AUIPC) in expandFunctionCall()
128 if (MI.getOpcode() == RISCV::PseudoTAIL) in expandFunctionCall()
130 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); in expandFunctionCall()
133 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); in expandFunctionCall()
145 assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 && in expandAddTPRel()
158 0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc())); in expandAddTPRel()
[all …]
/external/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
DRISCVAsmBackend.cpp71 static_assert((array_lengthof(Infos)) == RISCV::NumTargetFixupKinds, in getFixupKindInfo()
105 case RISCV::fixup_riscv_got_hi20: in shouldForceRelocation()
106 case RISCV::fixup_riscv_tls_got_hi20: in shouldForceRelocation()
107 case RISCV::fixup_riscv_tls_gd_hi20: in shouldForceRelocation()
111 return STI.getFeatureBits()[RISCV::FeatureRelax] || ForceRelocs; in shouldForceRelocation()
131 case RISCV::fixup_riscv_rvc_branch: in fixupNeedsRelaxationAdvanced()
135 case RISCV::fixup_riscv_rvc_jump: in fixupNeedsRelaxationAdvanced()
149 case RISCV::C_BEQZ: in relaxInstruction()
151 Res.setOpcode(RISCV::BEQ); in relaxInstruction()
153 Res.addOperand(MCOperand::createReg(RISCV::X0)); in relaxInstruction()
[all …]
DRISCVMCCodeEmitter.cpp119 if (MI.getOpcode() == RISCV::PseudoTAIL) { in expandFunctionCall()
121 Ra = RISCV::X6; in expandFunctionCall()
122 } else if (MI.getOpcode() == RISCV::PseudoCALLReg) { in expandFunctionCall()
125 } else if (MI.getOpcode() == RISCV::PseudoCALL) { in expandFunctionCall()
127 Ra = RISCV::X1; in expandFunctionCall()
128 } else if (MI.getOpcode() == RISCV::PseudoJump) { in expandFunctionCall()
139 TmpInst = MCInstBuilder(RISCV::AUIPC) in expandFunctionCall()
145 if (MI.getOpcode() == RISCV::PseudoTAIL || in expandFunctionCall()
146 MI.getOpcode() == RISCV::PseudoJump) in expandFunctionCall()
148 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); in expandFunctionCall()
[all …]
DRISCVELFObjectWriter.cpp65 case RISCV::fixup_riscv_pcrel_hi20: in getRelocType()
67 case RISCV::fixup_riscv_pcrel_lo12_i: in getRelocType()
69 case RISCV::fixup_riscv_pcrel_lo12_s: in getRelocType()
71 case RISCV::fixup_riscv_got_hi20: in getRelocType()
73 case RISCV::fixup_riscv_tls_got_hi20: in getRelocType()
75 case RISCV::fixup_riscv_tls_gd_hi20: in getRelocType()
77 case RISCV::fixup_riscv_jal: in getRelocType()
79 case RISCV::fixup_riscv_branch: in getRelocType()
81 case RISCV::fixup_riscv_rvc_jump: in getRelocType()
83 case RISCV::fixup_riscv_rvc_branch: in getRelocType()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.cpp36 : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP), in RISCVInstrInfo()
44 case RISCV::LB: in isLoadFromStackSlot()
45 case RISCV::LBU: in isLoadFromStackSlot()
46 case RISCV::LH: in isLoadFromStackSlot()
47 case RISCV::LHU: in isLoadFromStackSlot()
48 case RISCV::LW: in isLoadFromStackSlot()
49 case RISCV::FLW: in isLoadFromStackSlot()
50 case RISCV::LWU: in isLoadFromStackSlot()
51 case RISCV::LD: in isLoadFromStackSlot()
52 case RISCV::FLD: in isLoadFromStackSlot()
[all …]
DRISCVRegisterInfo.cpp29 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
30 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
31 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
32 static_assert(RISCV::F31_F == RISCV::F0_F + 31,
34 static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
35 static_assert(RISCV::F31_D == RISCV::F0_D + 31,
39 : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0, in RISCVRegisterInfo()
79 markSuperRegs(Reserved, RISCV::X0); // zero in getReservedRegs()
80 markSuperRegs(Reserved, RISCV::X2); // sp in getReservedRegs()
81 markSuperRegs(Reserved, RISCV::X3); // gp in getReservedRegs()
[all …]
DRISCVExpandPseudoInsts.cpp102 case RISCV::PseudoAtomicLoadNand32: in expandMI()
105 case RISCV::PseudoAtomicLoadNand64: in expandMI()
108 case RISCV::PseudoMaskedAtomicSwap32: in expandMI()
111 case RISCV::PseudoMaskedAtomicLoadAdd32: in expandMI()
113 case RISCV::PseudoMaskedAtomicLoadSub32: in expandMI()
115 case RISCV::PseudoMaskedAtomicLoadNand32: in expandMI()
118 case RISCV::PseudoMaskedAtomicLoadMax32: in expandMI()
121 case RISCV::PseudoMaskedAtomicLoadMin32: in expandMI()
124 case RISCV::PseudoMaskedAtomicLoadUMax32: in expandMI()
127 case RISCV::PseudoMaskedAtomicLoadUMin32: in expandMI()
[all …]
DRISCVMergeBaseOffset.cpp82 if (HiLUI.getOpcode() != RISCV::LUI || in detectLuiAddiGlobal()
90 if (LoADDI->getOpcode() != RISCV::ADDI || in detectLuiAddiGlobal()
137 assert((TailAdd.getOpcode() == RISCV::ADD) && "Expected ADD instruction!"); in matchLargeOffset()
147 if (OffsetTail.getOpcode() == RISCV::ADDI) { in matchLargeOffset()
157 if (OffsetLui.getOpcode() != RISCV::LUI || in matchLargeOffset()
168 } else if (OffsetTail.getOpcode() == RISCV::LUI) { in matchLargeOffset()
190 case RISCV::ADDI: { in detectAndFoldOffset()
197 case RISCV::ADD: { in detectAndFoldOffset()
212 case RISCV::LB: in detectAndFoldOffset()
213 case RISCV::LH: in detectAndFoldOffset()
[all …]
DRISCVISelLowering.cpp83 addRegisterClass(XLenVT, &RISCV::GPRRegClass); in RISCVTargetLowering()
86 addRegisterClass(MVT::f32, &RISCV::FPR32RegClass); in RISCVTargetLowering()
88 addRegisterClass(MVT::f64, &RISCV::FPR64RegClass); in RISCVTargetLowering()
93 setStackPointerRegisterToSaveRestore(RISCV::X2); in RISCVTargetLowering()
369 return RISCV::BEQ; in getBranchOpcodeForIntCondCode()
371 return RISCV::BNE; in getBranchOpcodeForIntCondCode()
373 return RISCV::BLT; in getBranchOpcodeForIntCondCode()
375 return RISCV::BGE; in getBranchOpcodeForIntCondCode()
377 return RISCV::BLTU; in getBranchOpcodeForIntCondCode()
379 return RISCV::BGEU; in getBranchOpcodeForIntCondCode()
[all …]
DRISCVISelDAGToDAG.cpp72 SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT); in selectImm()
75 if (Inst.Opc == RISCV::LUI) in selectImm()
76 Result = CurDAG->getMachineNode(RISCV::LUI, DL, XLenVT, SDImm); in selectImm()
118 RISCV::X0, XLenVT); in Select()
133 ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ADDI, DL, VT, TFI, Imm)); in Select()
153 CurDAG->SelectNodeTo(Node, RISCV::SRLIW, XLenVT, Op0.getOperand(0), in Select()
163 ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ReadCycleWide, DL, MVT::i32, in Select()
219 case RISCV::LB: in doPeepholeLoadStoreADDI()
220 case RISCV::LH: in doPeepholeLoadStoreADDI()
221 case RISCV::LW: in doPeepholeLoadStoreADDI()
[all …]
DRISCVFrameLowering.cpp81 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
86 unsigned Opc = RISCV::ADD; in adjustReg()
90 Opc = RISCV::SUB; in adjustReg()
93 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in adjustReg()
103 static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; } in getFPReg()
106 static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; } in getSPReg()
218 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg) in emitPrologue()
224 MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass); in emitPrologue()
225 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR) in emitPrologue()
228 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg) in emitPrologue()
[all …]
/external/llvm-project/llvm/lib/Target/RISCV/AsmParser/
DRISCVAsmParser.cpp67 bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); } in isRV64()
68 bool isRV32E() const { return getSTI().hasFeature(RISCV::FeatureRV32E); } in isRV32E()
232 !getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) { in RISCVAsmParser()
237 !getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) { in RISCVAsmParser()
324 return Kind == KindTy::Register && Reg.RegNum == RISCV::V0; in isV0Reg()
333 RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum); in isGPR()
956 assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register"); in convertFPR64ToFPR16()
957 return Reg - RISCV::F0_D + RISCV::F0_H; in convertFPR64ToFPR16()
961 assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register"); in convertFPR64ToFPR32()
962 return Reg - RISCV::F0_D + RISCV::F0_F; in convertFPR64ToFPR32()
[all …]
/external/llvm-project/clang/lib/Basic/Targets/
DRISCV.cpp190 return llvm::RISCV::checkCPUKind(llvm::RISCV::parseCPUKind(Name), in isValidCPUName()
196 llvm::RISCV::fillValidCPUArchList(Values, false); in fillValidCPUList()
200 return llvm::RISCV::checkTuneCPUKind( in isValidTuneCPUName()
201 llvm::RISCV::parseTuneCPUKind(Name, false), in isValidTuneCPUName()
207 llvm::RISCV::fillValidTuneCPUArchList(Values, false); in fillValidTuneCPUList()
211 return llvm::RISCV::checkCPUKind(llvm::RISCV::parseCPUKind(Name), in isValidCPUName()
217 llvm::RISCV::fillValidCPUArchList(Values, true); in fillValidCPUList()
221 return llvm::RISCV::checkTuneCPUKind( in isValidTuneCPUName()
222 llvm::RISCV::parseTuneCPUKind(Name, true), in isValidTuneCPUName()
228 llvm::RISCV::fillValidTuneCPUArchList(Values, true); in fillValidTuneCPUList()
/external/llvm-project/llvm/lib/Target/RISCV/Disassembler/
DRISCVDisassembler.cpp68 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; in DecodeGPRRegisterClass()
73 MCRegister Reg = RISCV::X0 + RegNo; in DecodeGPRRegisterClass()
84 MCRegister Reg = RISCV::F0_H + RegNo; in DecodeFPR16RegisterClass()
95 MCRegister Reg = RISCV::F0_F + RegNo; in DecodeFPR32RegisterClass()
106 MCRegister Reg = RISCV::F8_F + RegNo; in DecodeFPR32CRegisterClass()
117 MCRegister Reg = RISCV::F0_D + RegNo; in DecodeFPR64RegisterClass()
128 MCRegister Reg = RISCV::F8_D + RegNo; in DecodeFPR64CRegisterClass()
159 MCRegister Reg = RISCV::X8 + RegNo; in DecodeGPRCRegisterClass()
170 MCRegister Reg = RISCV::V0 + RegNo; in DecodeVRRegisterClass()
177 MCRegister Reg = RISCV::NoRegister; in decodeVMaskReg()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/AsmParser/
DRISCVAsmParser.cpp57 bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); } in isRV64()
58 bool isRV32E() const { return getSTI().hasFeature(RISCV::FeatureRV32E); } in isRV32E()
200 !getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) { in RISCVAsmParser()
205 !getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) { in RISCVAsmParser()
282 RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum); in isGPR()
771 assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register"); in convertFPR64ToFPR32()
772 return Reg - RISCV::F0_D + RISCV::F0_F; in convertFPR64ToFPR32()
783 RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg); in validateTargetOperandClass()
785 RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg); in validateTargetOperandClass()
1001 assert(!(RegNo >= RISCV::F0_F && RegNo <= RISCV::F31_F)); in matchRegisterNameHelper()
[all …]

123456