| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 2848 auto Rcp = B.buildInstr(AMDGPU::G_AMDGPU_RCP_IFLAG, {S32}, {Mad}); in emitReciprocalU64() local
2850 B.buildFMul(S32, Rcp, B.buildFConstant(S32, BitsToFloat(0x5f7ffffc))); in emitReciprocalU64()
2879 auto Rcp = B.buildMerge(S64, {RcpLo, RcpHi}); in legalizeUDIV_UREM64Impl() local
2884 auto MulLo1 = B.buildMul(S64, NegDenom, Rcp); in legalizeUDIV_UREM64Impl()
2885 auto MulHi1 = B.buildUMulH(S64, Rcp, MulLo1); in legalizeUDIV_UREM64Impl()
3259 auto Rcp = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S64}, false) in legalizeFDIV64() local
3263 auto Fma0 = B.buildFMA(S64, NegDivScale0, Rcp, One, Flags); in legalizeFDIV64()
3264 auto Fma1 = B.buildFMA(S64, Rcp, Fma0, Rcp, Flags); in legalizeFDIV64()
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| D | AMDGPUCodeGenPrepare.cpp | 1116 Function *Rcp = Intrinsic::getDeclaration(Mod, Intrinsic::amdgcn_rcp, F32Ty); in expandDivRem32() local
1117 Value *RcpY = Builder.CreateCall(Rcp, {FloatY}); in expandDivRem32()
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| D | AMDGPUISelLowering.cpp | 1814 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1); in LowerUDIVREM64() local
1815 SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp, in LowerUDIVREM64()
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| D | SIISelLowering.cpp | 8501 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0); in LowerFDIV64() local
8503 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One); in LowerFDIV64()
8505 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp); in LowerFDIV64()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 2152 auto Rcp = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S64}, false) in legalizeFDIV64() local
2156 auto Fma0 = B.buildFMA(S64, NegDivScale0, Rcp, One, Flags); in legalizeFDIV64()
2157 auto Fma1 = B.buildFMA(S64, Rcp, Fma0, Rcp, Flags); in legalizeFDIV64()
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| D | AMDGPUISelLowering.cpp | 1685 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1); in LowerUDIVREM64() local
1686 SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp, in LowerUDIVREM64()
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| D | SIISelLowering.cpp | 7823 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0); in LowerFDIV64() local
7825 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One); in LowerFDIV64()
7827 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp); in LowerFDIV64()
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| /external/swiftshader/src/Pipeline/ |
| D | ShaderCore.cpp | 227 return Rcp(x, pp ? Precision::Relaxed : Precision::Full, finite, exactAtPow2); in reciprocal()
239 return Rcp(abs, pp ? Precision::Relaxed : Precision::Full); in reciprocalSquareRoot()
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| D | SamplerCore.cpp | 1229 anisotropy = lod * Rcp(det, Precision::Relaxed); in computeLod2D()
1232 lod *= Rcp(anisotropy * anisotropy, Precision::Relaxed); in computeLod2D()
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| D | PixelRoutine.cpp | 166 WWWW = Rcp(WWWW, Precision::Relaxed); in quad()
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| /external/clang/include/clang/Basic/ |
| D | BuiltinsNVPTX.def | 212 // Rcp
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 2241 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0); in LowerFDIV64() local
2243 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One); in LowerFDIV64()
2245 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp); in LowerFDIV64()
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| /external/llvm-project/clang/include/clang/Basic/ |
| D | BuiltinsNVPTX.def | 221 // Rcp
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| /external/swiftshader/src/Reactor/ |
| D | Reactor.hpp | 2181 RValue<Float> Rcp(RValue<Float> x, Precision p = Precision::Full, bool finite = false, bool exactAt…
2352 RValue<Float4> Rcp(RValue<Float4> x, Precision p = Precision::Full, bool finite = false, bool exact…
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| D | Reactor.cpp | 4709 RValue<Float4> Rcp(RValue<Float4> x, Precision p, bool finite, bool exactAtPow2) in Rcp() function
4715 RValue<Float> Rcp(RValue<Float> x, Precision p, bool finite, bool exactAtPow2) in Rcp() function
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| /external/llvm/include/llvm/IR/ |
| D | IntrinsicsNVVM.td | 373 // Rcp
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | IntrinsicsNVVM.td | 628 // Rcp
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| /external/llvm-project/llvm/include/llvm/IR/ |
| D | IntrinsicsNVVM.td | 621 // Rcp
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXIntrinsics.td | 476 // Rcp
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| /external/llvm-project/llvm/lib/Target/NVPTX/ |
| D | NVPTXIntrinsics.td | 601 // Rcp
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXIntrinsics.td | 601 // Rcp
|