/external/llvm/lib/Target/ARM/ |
D | ARMFastISel.cpp | 195 SmallVectorImpl<unsigned> &RegArgs, 1874 SmallVectorImpl<unsigned> &RegArgs, in ProcessCallArgs() argument 1978 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs() 1993 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs() 1994 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs() 2236 SmallVector<unsigned, 4> RegArgs; in ARMEmitLibcall() local 2239 RegArgs, CC, NumBytes, false)) in ARMEmitLibcall() 2261 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) in ARMEmitLibcall() 2262 MIB.addReg(RegArgs[i], RegState::Implicit); in ARMEmitLibcall() 2370 SmallVector<unsigned, 4> RegArgs; in SelectCall() local [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMFastISel.cpp | 225 SmallVectorImpl<Register> &RegArgs, 1891 SmallVectorImpl<Register> &RegArgs, in ProcessCallArgs() argument 1995 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs() 2011 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs() 2012 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs() 2251 SmallVector<Register, 4> RegArgs; in ARMEmitLibcall() local 2254 RegArgs, CC, NumBytes, false)) in ARMEmitLibcall() 2276 for (Register R : RegArgs) in ARMEmitLibcall() 2384 SmallVector<Register, 4> RegArgs; in SelectCall() local 2387 RegArgs, CC, NumBytes, isVarArg)) in SelectCall() [all …]
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/external/llvm-project/llvm/lib/Target/ARM/ |
D | ARMFastISel.cpp | 224 SmallVectorImpl<Register> &RegArgs, 1878 SmallVectorImpl<Register> &RegArgs, in ProcessCallArgs() argument 1982 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs() 1998 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs() 1999 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs() 2248 SmallVector<Register, 4> RegArgs; in ARMEmitLibcall() local 2251 RegArgs, CC, NumBytes, false)) in ARMEmitLibcall() 2273 for (Register R : RegArgs) in ARMEmitLibcall() 2379 SmallVector<Register, 4> RegArgs; in SelectCall() local 2382 RegArgs, CC, NumBytes, isVarArg)) in SelectCall() [all …]
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/external/llvm/lib/Target/PowerPC/ |
D | PPCFastISel.cpp | 184 SmallVectorImpl<unsigned> &RegArgs, 1281 SmallVectorImpl<unsigned> &RegArgs, in processCallArgs() argument 1385 RegArgs.push_back(ArgReg); in processCallArgs() 1546 SmallVector<unsigned, 8> RegArgs; in fastLowerCall() local 1550 RegArgs, CC, NumBytes, IsVarArg)) in fastLowerCall() 1577 for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II) in fastLowerCall() 1578 MIB.addReg(RegArgs[II], RegState::Implicit); in fastLowerCall()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
D | PPCFastISel.cpp | 192 SmallVectorImpl<unsigned> &RegArgs, 1378 SmallVectorImpl<unsigned> &RegArgs, in processCallArgs() argument 1482 RegArgs.push_back(ArgReg); in processCallArgs() 1636 SmallVector<unsigned, 8> RegArgs; in fastLowerCall() local 1640 RegArgs, CC, NumBytes, IsVarArg)) in fastLowerCall() 1667 for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II) in fastLowerCall() 1668 MIB.addReg(RegArgs[II], RegState::Implicit); in fastLowerCall()
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/external/llvm-project/llvm/lib/Target/PowerPC/ |
D | PPCFastISel.cpp | 193 SmallVectorImpl<unsigned> &RegArgs, 1381 SmallVectorImpl<unsigned> &RegArgs, in processCallArgs() argument 1485 RegArgs.push_back(ArgReg); in processCallArgs() 1646 SmallVector<unsigned, 8> RegArgs; in fastLowerCall() local 1650 RegArgs, CC, NumBytes, IsVarArg)) in fastLowerCall() 1677 for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II) in fastLowerCall() 1678 MIB.addReg(RegArgs[II], RegState::Implicit); in fastLowerCall()
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/external/swiftshader/third_party/subzero/src/ |
D | IceTargetLoweringMIPS32.cpp | 3340 CfgVector<Variable *> RegArgs; in lowerCall() local 3368 RegArgs.emplace_back( in lowerCall() 3522 RegArgs.emplace_back(legalizeToReg(FPArg.first, FPArg.second)); in lowerCall() 3525 RegArgs.emplace_back(legalizeToReg(GPRArg.first, GPRArg.second)); in lowerCall() 3532 for (auto *RegArg : RegArgs) { in lowerCall()
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D | IceTargetLoweringARM32.cpp | 3824 CfgVector<Variable *> RegArgs; in lowerCall() local 3826 RegArgs.emplace_back(legalizeToReg(FPArg.first, FPArg.second)); in lowerCall() 3829 RegArgs.emplace_back(legalizeToReg(GPRArg.first, GPRArg.second)); in lowerCall() 3836 for (auto *RegArg : RegArgs) { in lowerCall()
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