| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 856 int64_t RegLo, RegHi; in ParseAMDGPURegister() local
870 RegHi = RegLo; in ParseAMDGPURegister()
872 if (getParser().parseAbsoluteExpression(RegHi)) in ParseAMDGPURegister()
880 RegWidth = (RegHi - RegLo) + 1; in ParseAMDGPURegister()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 2422 Register RegHi = RegLo + 1; in LowerReturn() local
2425 STI.isRegisterReservedByUser(RegHi)) in LowerReturn()
2433 Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue); in LowerReturn()
2435 RetOps.push_back(DAG.getRegister(RegHi, MVT::i32)); in LowerReturn()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2144 int64_t RegLo, RegHi; in ParseRegRange() local
2152 if (!parseExpr(RegHi)) in ParseRegRange()
2155 RegHi = RegLo; in ParseRegRange()
2161 if (!isUInt<32>(RegLo) || !isUInt<32>(RegHi) || RegLo > RegHi) in ParseRegRange()
2165 Width = (RegHi - RegLo) + 1; in ParseRegRange()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2304 int64_t RegLo, RegHi; in ParseRegRange() local
2316 if (!parseExpr(RegHi)) in ParseRegRange()
2319 RegHi = RegLo; in ParseRegRange()
2330 if (!isUInt<32>(RegHi)) { in ParseRegRange()
2335 if (RegLo > RegHi) { in ParseRegRange()
2341 Width = (RegHi - RegLo) + 1; in ParseRegRange()
|
| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 3125 Register RegHi = RegLo + 1; in LowerReturn() local
3128 STI.isRegisterReservedByUser(RegHi)) in LowerReturn()
3136 Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue); in LowerReturn()
3138 RetOps.push_back(DAG.getRegister(RegHi, MVT::i32)); in LowerReturn()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 913 unsigned RegHi = TRI->getSubReg(Reg, AMDGPU::sub1); in expandPostRAPseudo() local
925 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi) in expandPostRAPseudo()
926 .addReg(RegHi) in expandPostRAPseudo()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 874 unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
876 MIB.addReg(RegHi, Flags | getKillRegState(Reg.isDead())); in addExclusiveRegPair()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 1040 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
1042 MIB.addReg(RegHi, Flags); in addExclusiveRegPair()
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 3870 Variable *RegHi, *RegLo; in lowerCast() local
3875 RegHi = legalizeToReg(Ctx->getConstantInt32(Upper32Bits)); in lowerCast()
3876 _mov(Dest, RegHi, RegLo); in lowerCast()
3880 auto *RegHi = legalizeToReg(hiOperand(Var64On32)); in lowerCast() local
3881 _mov(Dest, RegHi, RegLo); in lowerCast()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 1665 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair() local
1667 MIB.addReg(RegHi, Flags); in addExclusiveRegPair()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1516 Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1); in expandPostRAPseudo() local
1529 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi) in expandPostRAPseudo()
1530 .addReg(RegHi); in expandPostRAPseudo()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1855 Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1); in expandPostRAPseudo() local
1868 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi) in expandPostRAPseudo()
1869 .addReg(RegHi); in expandPostRAPseudo()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 3586 unsigned RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC); in LowerFormalArguments_32SVR4() local
3588 SDValue ArgValueHi = DAG.getCopyFromReg(Chain, dl, RegHi, MVT::i32); in LowerFormalArguments_32SVR4()
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 3832 unsigned RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC); in LowerFormalArguments_32SVR4() local
3834 SDValue ArgValueHi = DAG.getCopyFromReg(Chain, dl, RegHi, MVT::i32); in LowerFormalArguments_32SVR4()
|