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Searched refs:RegMaskSlots (Results 1 – 9 of 9) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DInterferenceCache.cpp161 ArrayRef<SlotIndex> RegMaskSlots; in update() local
193 RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum); in update()
196 for (unsigned i = 0, e = RegMaskSlots.size(); in update()
197 i != e && RegMaskSlots[i] < Limit; ++i) in update()
200 BI->First = RegMaskSlots[i]; in update()
253 for (unsigned i = RegMaskSlots.size(); in update()
254 i && RegMaskSlots[i-1].getDeadSlot() > Limit; --i) in update()
258 BI->Last = RegMaskSlots[i-1].getDeadSlot(); in update()
DLiveIntervals.cpp113 RegMaskSlots.clear(); in releaseMemory()
170 for (SlotIndex Idx : RegMaskSlots) in print()
222 RMB.first = RegMaskSlots.size(); in computeRegMasks()
226 RegMaskSlots.push_back(Indexes->getMBBStartIdx(&MBB)); in computeRegMasks()
234 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot()); in computeRegMasks()
244 RegMaskSlots.push_back( in computeRegMasks()
250 RMB.second = RegMaskSlots.size() - RMB.first; in computeRegMasks()
1398 llvm::lower_bound(LIS.RegMaskSlots, OldIdx); in updateRegMaskSlots()
1399 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() && in updateRegMaskSlots()
1402 assert((RI == LIS.RegMaskSlots.begin() || in updateRegMaskSlots()
[all …]
/external/llvm/lib/CodeGen/
DInterferenceCache.cpp150 ArrayRef<SlotIndex> RegMaskSlots; in update() local
182 RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum); in update()
185 for (unsigned i = 0, e = RegMaskSlots.size(); in update()
186 i != e && RegMaskSlots[i] < Limit; ++i) in update()
189 BI->First = RegMaskSlots[i]; in update()
242 for (unsigned i = RegMaskSlots.size(); in update()
243 i && RegMaskSlots[i-1].getDeadSlot() > Limit; --i) in update()
247 BI->Last = RegMaskSlots[i-1].getDeadSlot(); in update()
DLiveIntervalAnalysis.cpp99 RegMaskSlots.clear(); in releaseMemory()
162 for (unsigned i = 0, e = RegMaskSlots.size(); i != e; ++i) in print()
163 OS << ' ' << RegMaskSlots[i]; in print()
212 RMB.first = RegMaskSlots.size(); in computeRegMasks()
216 RegMaskSlots.push_back(Indexes->getMBBStartIdx(&MBB)); in computeRegMasks()
224 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot()); in computeRegMasks()
234 RegMaskSlots.push_back( in computeRegMasks()
240 RMB.second = RegMaskSlots.size() - RMB.first; in computeRegMasks()
1298 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(), in updateRegMaskSlots()
1300 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() && in updateRegMaskSlots()
[all …]
/external/llvm-project/llvm/lib/CodeGen/
DInterferenceCache.cpp157 ArrayRef<SlotIndex> RegMaskSlots; in update() local
189 RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum); in update()
192 for (unsigned i = 0, e = RegMaskSlots.size(); in update()
193 i != e && RegMaskSlots[i] < Limit; ++i) in update()
196 BI->First = RegMaskSlots[i]; in update()
249 for (unsigned i = RegMaskSlots.size(); in update()
250 i && RegMaskSlots[i-1].getDeadSlot() > Limit; --i) in update()
254 BI->Last = RegMaskSlots[i-1].getDeadSlot(); in update()
DLiveIntervals.cpp111 RegMaskSlots.clear(); in releaseMemory()
168 for (SlotIndex Idx : RegMaskSlots) in print()
220 RMB.first = RegMaskSlots.size(); in computeRegMasks()
224 RegMaskSlots.push_back(Indexes->getMBBStartIdx(&MBB)); in computeRegMasks()
233 RegMaskSlots.push_back(Indexes->getMBBStartIdx(&MBB)); in computeRegMasks()
241 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot()); in computeRegMasks()
251 RegMaskSlots.push_back( in computeRegMasks()
257 RMB.second = RegMaskSlots.size() - RMB.first; in computeRegMasks()
1418 llvm::lower_bound(LIS.RegMaskSlots, OldIdx); in updateRegMaskSlots()
1419 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() && in updateRegMaskSlots()
[all …]
/external/llvm/include/llvm/CodeGen/
DLiveIntervalAnalysis.h72 SmallVector<SlotIndex, 8> RegMaskSlots; variable
239 RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0)); in insertMBBInMaps()
331 ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; } in getRegMaskSlots()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DLiveIntervals.h72 SmallVector<SlotIndex, 8> RegMaskSlots; variable
263 RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0)); in insertMBBInMaps()
351 ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; } in getRegMaskSlots()
/external/llvm-project/llvm/include/llvm/CodeGen/
DLiveIntervals.h72 SmallVector<SlotIndex, 8> RegMaskSlots; variable
264 RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0));
352 ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; } in getRegMaskSlots()