| /external/llvm-project/clang/unittests/StaticAnalyzer/ |
| D | TestReturnValueUnderConstruction.cpp | 39 const auto *RetReg = cast<TypedValueRegion>(RetVal->getAsRegion()); in checkPostCall() local
41 ASSERT_EQ(OrigExpr->getType(), RetReg->getValueType()); in checkPostCall()
|
| /external/llvm-project/clang/lib/StaticAnalyzer/Checkers/ |
| D | DynamicTypePropagation.cpp | 312 const MemRegion *RetReg = Call.getReturnValue().getAsRegion(); in checkPostCall() local
313 if (!RetReg) in checkPostCall()
345 C.addTransition(setDynamicTypeInfo(State, RetReg, DynResTy, false)); in checkPostCall()
355 C.addTransition(setDynamicTypeInfo(State, RetReg, RecDynType)); in checkPostCall()
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| /external/clang/lib/StaticAnalyzer/Checkers/ |
| D | DynamicTypePropagation.cpp | 207 const MemRegion *RetReg = Call.getReturnValue().getAsRegion(); in checkPostCall() local
208 if (!RetReg) in checkPostCall()
231 C.addTransition(setDynamicTypeInfo(State, RetReg, DynResTy, false)); in checkPostCall()
241 C.addTransition(setDynamicTypeInfo(State, RetReg, RecDynType)); in checkPostCall()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 1630 unsigned RetReg = VA.getLocReg(); in SelectRet() local
1639 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg); in SelectRet()
1641 RetRegs.push_back(RetReg); in SelectRet()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 1720 Register RetReg = VA.getLocReg(); in SelectRet() local
1729 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg); in SelectRet()
1731 RetRegs.push_back(RetReg); in SelectRet()
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 1727 Register RetReg = VA.getLocReg(); in SelectRet() local
1736 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg); in SelectRet()
1738 RetRegs.push_back(RetReg); in SelectRet()
|
| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1259 unsigned RetReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; in X86SelectRet() local
1261 TII.get(TargetOpcode::COPY), RetReg).addReg(Reg); in X86SelectRet()
1262 RetRegs.push_back(RetReg); in X86SelectRet()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1270 unsigned RetReg = Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX; in X86SelectRet() local
1272 TII.get(TargetOpcode::COPY), RetReg).addReg(Reg); in X86SelectRet()
1273 RetRegs.push_back(RetReg); in X86SelectRet()
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1291 unsigned RetReg = Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX; in X86SelectRet() local
1293 TII.get(TargetOpcode::COPY), RetReg).addReg(Reg); in X86SelectRet()
1294 RetRegs.push_back(RetReg); in X86SelectRet()
|
| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 2679 unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT)); in LowerRETURNADDR() local
2680 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); in LowerRETURNADDR()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 2673 unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT)); in LowerRETURNADDR() local
2674 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); in LowerRETURNADDR()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 2682 unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT)); in LowerRETURNADDR() local
2683 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); in LowerRETURNADDR()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.td | 1336 Register RetReg, RegisterOperand ResRO = RO>:
1338 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 3942 for (unsigned RetReg : RetRegs) in selectRet() local
3943 MIB.addReg(RetReg, RegState::Implicit); in selectRet()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 3764 for (unsigned RetReg : RetRegs) in selectRet() local
3765 MIB.addReg(RetReg, RegState::Implicit); in selectRet()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 3935 for (unsigned RetReg : RetRegs) in selectRet() local
3936 MIB.addReg(RetReg, RegState::Implicit); in selectRet()
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.td | 1577 Register RetReg, RegisterOperand ResRO = RO>:
1579 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)> {
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.td | 1577 Register RetReg, RegisterOperand ResRO = RO>:
1579 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)> {
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 3546 Variable *RetReg = nullptr; in lowerCall() local
3547 NewCall = InstMIPS32Call::create(Func, RetReg, CallTarget); in lowerCall()
|