| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 906 bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc, in SelectMUBUFScratch() argument
914 Rsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32); in SelectMUBUFScratch()
952 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | in SelectMUBUFOffset() local
959 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); in SelectMUBUFOffset()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 4330 const DebugLoc &DL, MachineOperand &Rsrc) { in emitLoadSRsrcFromVGPRLoop() argument
4345 Register VRsrc = Rsrc.getReg(); in emitLoadSRsrcFromVGPRLoop()
4346 unsigned VRsrcUndef = getUndefRegState(Rsrc.isUndef()); in emitLoadSRsrcFromVGPRLoop()
4379 Rsrc.setReg(SRsrc); in emitLoadSRsrcFromVGPRLoop()
4380 Rsrc.setIsKill(true); in emitLoadSRsrcFromVGPRLoop()
4412 MachineOperand &Rsrc, MachineDominatorTree *MDT) { in loadSRsrcFromVGPR() argument
4472 emitLoadSRsrcFromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, Rsrc); in loadSRsrcFromVGPR()
4481 extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) { in extractRsrcPtr() argument
4488 TII.buildExtractSubReg(MI, MRI, Rsrc, &AMDGPU::VReg_128RegClass, in extractRsrcPtr()
4679 MachineOperand *Rsrc = &MI.getOperand(RsrcIdx); in legalizeOperands() local
[all …]
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| D | SIISelLowering.h | 62 SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
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| D | AMDGPUISelDAGToDAG.cpp | 1498 SDValue Addr, SDValue &Rsrc, in SelectMUBUFScratchOffen() argument
1506 Rsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32); in SelectMUBUFScratchOffen()
1607 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | in SelectMUBUFOffset() local
1614 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); in SelectMUBUFOffset()
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| D | SIISelLowering.cpp | 5657 SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, in lowerSBuffer() argument
5674 Rsrc, in lowerSBuffer()
5715 Rsrc, // rsrc in lowerSBuffer()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 4835 const DebugLoc &DL, MachineOperand &Rsrc) { in emitLoadSRsrcFromVGPRLoop() argument
4853 Register VRsrc = Rsrc.getReg(); in emitLoadSRsrcFromVGPRLoop()
4854 unsigned VRsrcUndef = getUndefRegState(Rsrc.isUndef()); in emitLoadSRsrcFromVGPRLoop()
4856 unsigned RegSize = TRI->getRegSizeInBits(Rsrc.getReg(), MRI); in emitLoadSRsrcFromVGPRLoop()
4917 Rsrc.setReg(SRsrc); in emitLoadSRsrcFromVGPRLoop()
4918 Rsrc.setIsKill(true); in emitLoadSRsrcFromVGPRLoop()
4943 MachineOperand &Rsrc, MachineDominatorTree *MDT, in loadSRsrcFromVGPR() argument
5014 emitLoadSRsrcFromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, Rsrc); in loadSRsrcFromVGPR()
5024 extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) { in extractRsrcPtr() argument
5031 TII.buildExtractSubReg(MI, MRI, Rsrc, &AMDGPU::VReg_128RegClass, in extractRsrcPtr()
[all …]
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| D | SIISelLowering.h | 63 SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
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| D | AMDGPUISelDAGToDAG.cpp | 1558 SDValue Addr, SDValue &Rsrc, in SelectMUBUFScratchOffen() argument
1566 Rsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32); in SelectMUBUFScratchOffen()
1671 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | in SelectMUBUFOffset() local
1678 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0); in SelectMUBUFOffset()
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| D | SIISelLowering.cpp | 6322 SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, in lowerSBuffer() argument
6339 Rsrc, in lowerSBuffer()
6377 Rsrc, // rsrc in lowerSBuffer()
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | mubuf-legalize-operands.ll | 6 ; Test that we correctly legalize VGPR Rsrc operands in MUBUF instructions.
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| D | mubuf-legalize-operands.mir | 6 # Test that we correctly legalize VGPR Rsrc operands in MUBUF instructions.
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