| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSERegisterInfo.cpp | 86 case Mips::SCD: in getLoadStoreOffsetSizeInBits()
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| D | MipsExpandPseudo.cpp | 236 SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; in expandAtomicCmpSwap()
620 SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; in expandAtomicBinOp()
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| D | Mips32r6InstrFormats.td | 60 // The spec occasionally names this value LL, LLD, SC, or SCD.
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| D | Mips64InstrInfo.td | 251 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
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| D | MipsScheduleGeneric.td | 690 def : InstRW<[GenericWriteStore], (instrs SD, SC64, SCD, SB64, SH64, SW64,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSERegisterInfo.cpp | 86 case Mips::SCD: in getLoadStoreOffsetSizeInBits()
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| D | MipsExpandPseudo.cpp | 236 SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; in expandAtomicCmpSwap()
620 SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; in expandAtomicBinOp()
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| D | Mips32r6InstrFormats.td | 60 // The spec occasionally names this value LL, LLD, SC, or SCD.
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| D | Mips64InstrInfo.td | 251 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
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| D | MipsScheduleGeneric.td | 690 def : InstRW<[GenericWriteStore], (instrs SD, SC64, SCD, SB64, SH64, SW64,
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| /external/llvm/lib/Target/Mips/ |
| D | Mips32r6InstrFormats.td | 61 // The spec occasionally names this value LL, LLD, SC, or SCD.
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| D | Mips64InstrInfo.td | 223 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
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| D | MipsISelLowering.cpp | 1135 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; in emitAtomicBinary()
1422 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; in emitAtomicCmpSwap()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineScheduler.cpp | 1623 for (auto &SCD : StoreChains) in apply() local
1624 clusterNeighboringMemOps(SCD.second, DAG); in apply()
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| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 1278 Inst.getOpcode() == Mips::SCD) in DecodeMem()
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1444 3968802U, // SCD
3233 0U, // SCD
4851 // SC, SCD, SCD_R6, SC_MM, SC_R6
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| D | MipsGenDisassemblerTables.inc | 4784 /* 2320 */ MCD_OPC_Decode, 147, 11, 217, 1, // Opcode: SCD
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| /external/llvm-project/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 1544 Inst.getOpcode() == Mips::SCD) in DecodeMem()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 1544 Inst.getOpcode() == Mips::SCD) in DecodeMem()
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| /external/llvm-project/clang/lib/Sema/ |
| D | SemaOpenMP.cpp | 3669 const Decl *SCD = SC.getAssociatedDeclaration(); in VisitMemberExpr() local
3671 SCD = SCD ? SCD->getCanonicalDecl() : nullptr; in VisitMemberExpr()
3672 if (SCD != CCD) in VisitMemberExpr()
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmWriter.inc | 3566 4493344U, // SCD
6320 0U, // SCD
6932 // SC, SC64, SC64_R6, SCD, SCD_R6, SCE, SCE_MM, SC_MM, SC_MMR6, SC_R6
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| D | MipsGenMCCodeEmitter.inc | 2338 UINT64_C(4026531840), // SCD
7649 case Mips::SCD: {
11800 CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SCD = 2325
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| D | MipsGenInstrInfo.inc | 2340 SCD = 2325,
7186 …nmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr }, // Inst #2325 = SCD
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| D | MipsGenDisassemblerTables.inc | 7101 /* 1239 */ MCD::OPC_Decode, 149, 18, 130, 1, // Opcode: SCD
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| /external/toolchain-utils/android_bench_suite/panorama_input/ |
| D | test_011.ppm | 2401 bOQiYZK;<QFEODCPEDH=<SCD]LMfYYgZZF<;-"!0&%1'&
3950 SCDopɹ�������Ʒ��½���������������m][eTS�����������������Ÿ�����ѽ����������_OM'R?<;(%
4089 …��������������������������������������������d[XD<8 6.*;0-������ͽ�ó�SCD)K;<�|}J:;�z;����…
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