1 /*
2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
3  * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #include <string.h>
9 
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <lib/mmio.h>
13 
14 #include <mce.h>
15 #include <tegra_def.h>
16 #include <tegra_private.h>
17 
18 #define SCRATCH_SECURE_RSV1_SCRATCH_0	0x658U
19 #define SCRATCH_SECURE_RSV1_SCRATCH_1	0x65CU
20 
21 #define CPU_RESET_MODE_AA64		1U
22 
23 /*******************************************************************************
24  * Setup secondary CPU vectors
25  ******************************************************************************/
plat_secondary_setup(void)26 void plat_secondary_setup(void)
27 {
28 	uint32_t addr_low, addr_high;
29 
30 	INFO("Setting up secondary CPU boot\n");
31 
32 	/* TZDRAM base will be used as the "resume" address */
33 	addr_low = (uintptr_t)&tegra_secure_entrypoint | CPU_RESET_MODE_AA64;
34 	addr_high = (uintptr_t)(((uintptr_t)&tegra_secure_entrypoint >> 32U) & 0x7ffU);
35 
36 	/* save reset vector to be used during SYSTEM_SUSPEND exit */
37 	mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO,
38 			addr_low);
39 	mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI,
40 			addr_high);
41 }
42