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/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypes.h93 SmallDenseMap<SDValue, TableId, 8> ValueToIdMap;
94 SmallDenseMap<TableId, SDValue, 8> IdToValueMap;
140 TableId getTableId(SDValue V) { in getTableId()
159 const SDValue &getSDValue(TableId &Id) { in getSDValue()
183 TableId NewId = getTableId(SDValue(New, i)); in NoteDeletion()
184 TableId OldId = getTableId(SDValue(Old, i)); in NoteDeletion()
204 ValueToIdMap.erase(SDValue(Old, i)); in NoteDeletion()
212 void AnalyzeNewValue(SDValue &Val);
215 void RemapValue(SDValue &V);
218 SDValue BitConvertToInteger(SDValue Op);
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/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypes.h97 SmallDenseMap<SDValue, SDValue, 8> PromotedIntegers;
101 SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> ExpandedIntegers;
105 SmallDenseMap<SDValue, SDValue, 8> SoftenedFloats;
109 SmallDenseMap<SDValue, SDValue, 8> PromotedFloats;
113 SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> ExpandedFloats;
117 SmallDenseMap<SDValue, SDValue, 8> ScalarizedVectors;
121 SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> SplitVectors;
125 SmallDenseMap<SDValue, SDValue, 8> WidenedVectors;
129 SmallDenseMap<SDValue, SDValue, 8> ReplacedValues;
152 ReplacedValues[SDValue(Old, i)] = SDValue(New, i); in NoteDeletion()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypes.h93 SmallDenseMap<SDValue, TableId, 8> ValueToIdMap;
94 SmallDenseMap<TableId, SDValue, 8> IdToValueMap;
136 TableId getTableId(SDValue V) { in getTableId()
155 const SDValue &getSDValue(TableId &Id) { in getSDValue()
176 TableId NewId = getTableId(SDValue(New, i)); in NoteDeletion()
177 TableId OldId = getTableId(SDValue(Old, i)); in NoteDeletion()
183 ValueToIdMap.erase(SDValue(Old, i)); in NoteDeletion()
200 void AnalyzeNewValue(SDValue &Val);
203 void RemapValue(SDValue &V);
206 SDValue BitConvertToInteger(SDValue Op);
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/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonISelLowering.h122 bool IsEligibleForTailCallOptimization(SDValue Callee,
125 const SmallVectorImpl<SDValue> &OutVals,
139 bool hasBitTest(SDValue X, SDValue Y) const override;
158 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
159 void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
161 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
166 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
167 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
168 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
169 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelLowering.h115 bool IsEligibleForTailCallOptimization(SDValue Callee,
118 const SmallVectorImpl<SDValue> &OutVals,
132 bool hasBitTest(SDValue X, SDValue Y) const override;
151 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
152 void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
154 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
159 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
160 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
161 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
162 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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/external/llvm-project/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.h35 unsigned getMSACtrlReg(const SDValue RegIdx) const;
45 bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const;
46 bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
50 bool selectAddrRegImm(SDValue Addr, SDValue &Base,
51 SDValue &Offset) const override;
53 bool selectAddrDefault(SDValue Addr, SDValue &Base,
54 SDValue &Offset) const override;
56 bool selectIntAddr(SDValue Addr, SDValue &Base,
57 SDValue &Offset) const override;
59 bool selectAddrRegImm9(SDValue Addr, SDValue &Base,
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DMipsISelDAGToDAG.h58 virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
59 SDValue &Offset) const;
62 virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
63 SDValue &Offset) const;
66 virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
67 SDValue &Offset) const;
69 virtual bool selectIntAddr11MM(SDValue Addr, SDValue &Base,
70 SDValue &Offset) const;
72 virtual bool selectIntAddr12MM(SDValue Addr, SDValue &Base,
73 SDValue &Offset) const;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.h35 unsigned getMSACtrlReg(const SDValue RegIdx) const;
45 bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const;
46 bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
50 bool selectAddrRegImm(SDValue Addr, SDValue &Base,
51 SDValue &Offset) const override;
53 bool selectAddrDefault(SDValue Addr, SDValue &Base,
54 SDValue &Offset) const override;
56 bool selectIntAddr(SDValue Addr, SDValue &Base,
57 SDValue &Offset) const override;
59 bool selectAddrRegImm9(SDValue Addr, SDValue &Base,
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DMipsISelDAGToDAG.h58 virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
59 SDValue &Offset) const;
62 virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
63 SDValue &Offset) const;
66 virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
67 SDValue &Offset) const;
69 virtual bool selectIntAddr11MM(SDValue Addr, SDValue &Base,
70 SDValue &Offset) const;
72 virtual bool selectIntAddr12MM(SDValue Addr, SDValue &Base,
73 SDValue &Offset) const;
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/external/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.h34 unsigned getMSACtrlReg(const SDValue RegIdx) const;
42 void selectAddESubE(unsigned MOp, SDValue InFlag, SDValue CmpLHS,
45 bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const;
46 bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
49 bool selectAddrRegImm(SDValue Addr, SDValue &Base,
50 SDValue &Offset) const override;
52 bool selectAddrDefault(SDValue Addr, SDValue &Base,
53 SDValue &Offset) const override;
55 bool selectIntAddr(SDValue Addr, SDValue &Base,
56 SDValue &Offset) const override;
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DMipsISelDAGToDAG.h57 virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
58 SDValue &Offset) const;
61 virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
62 SDValue &Offset) const;
65 virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
66 SDValue &Offset) const;
68 virtual bool selectIntAddr11MM(SDValue Addr, SDValue &Base,
69 SDValue &Offset) const;
71 virtual bool selectIntAddr12MM(SDValue Addr, SDValue &Base,
72 SDValue &Offset) const;
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DSelectionDAGTargetInfo.h51 virtual SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, in EmitTargetCodeForMemcpy()
52 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemcpy()
53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy()
58 return SDValue(); in EmitTargetCodeForMemcpy()
67 virtual SDValue EmitTargetCodeForMemmove( in EmitTargetCodeForMemmove()
68 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, in EmitTargetCodeForMemmove()
69 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove()
71 return SDValue(); in EmitTargetCodeForMemmove()
80 virtual SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, in EmitTargetCodeForMemset()
81 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemset()
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DSelectionDAG.h247 SDValue Root;
384 void createOperands(SDNode *Node, ArrayRef<SDValue> Vals);
482 const SDValue &getRoot() const { return Root; }
485 SDValue getEntryNode() const {
486 return SDValue(const_cast<SDNode *>(&EntryNode), 0);
491 const SDValue &setRoot(SDValue N) {
586 SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT,
588 SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
591 SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget = false,
597 SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
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/external/llvm-project/llvm/include/llvm/CodeGen/
DSelectionDAGTargetInfo.h51 virtual SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, in EmitTargetCodeForMemcpy()
52 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemcpy()
53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy()
58 return SDValue(); in EmitTargetCodeForMemcpy()
67 virtual SDValue EmitTargetCodeForMemmove( in EmitTargetCodeForMemmove()
68 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, in EmitTargetCodeForMemmove()
69 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, in EmitTargetCodeForMemmove()
71 return SDValue(); in EmitTargetCodeForMemmove()
80 virtual SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, in EmitTargetCodeForMemset()
81 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemset()
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DSelectionDAG.h247 SDValue Root;
408 void createOperands(SDNode *Node, ArrayRef<SDValue> Vals);
520 const SDValue &getRoot() const { return Root; }
523 SDValue getEntryNode() const {
524 return SDValue(const_cast<SDNode *>(&EntryNode), 0);
529 const SDValue &setRoot(SDValue N) {
624 SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT,
626 SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
629 SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget = false,
635 SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
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/external/llvm/include/llvm/CodeGen/
DSelectionDAGTargetInfo.h49 virtual SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, in EmitTargetCodeForMemcpy()
50 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemcpy()
51 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy()
56 return SDValue(); in EmitTargetCodeForMemcpy()
65 virtual SDValue EmitTargetCodeForMemmove( in EmitTargetCodeForMemmove()
66 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, in EmitTargetCodeForMemmove()
67 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove()
69 return SDValue(); in EmitTargetCodeForMemmove()
78 virtual SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, in EmitTargetCodeForMemset()
79 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemset()
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DSelectionDAG.h192 SDValue Root;
287 void createOperands(SDNode *Node, ArrayRef<SDValue> Vals) {
376 const SDValue &getRoot() const { return Root; }
379 SDValue getEntryNode() const {
380 return SDValue(const_cast<SDNode *>(&EntryNode), 0);
385 const SDValue &setRoot(SDValue N) {
477 SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT,
479 SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
481 SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
483 SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL,
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/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.h31 SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
32 const SDValue &InitPtr,
33 SDValue Chain,
35 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
36 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
40 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
44 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
45 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
46 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
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/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCISelLowering.h664 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
727 bool hasAndNotCompare(SDValue) const override { in hasAndNotCompare() argument
737 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps,
753 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
754 SDValue &Offset,
760 bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index,
767 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
776 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
779 bool SelectAddressRegImm34(SDValue N, SDValue &Disp, SDValue &Base,
784 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCISelLowering.h606 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
669 bool hasAndNotCompare(SDValue) const override { in hasAndNotCompare() argument
703 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
704 SDValue &Offset,
710 bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index,
717 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
726 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
732 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
739 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
744 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIISelLowering.h40 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
41 SDValue Chain, uint64_t Offset) const;
42 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
43 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
44 const SDLoc &SL, SDValue Chain,
48 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
49 const SDLoc &SL, SDValue Chain,
51 SDValue getPreloadedValue(SelectionDAG &DAG,
56 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
58 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
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DAMDGPUISelLowering.h36 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
39 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
40 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
44 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
45 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
49 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
51 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
52 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
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/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIISelLowering.h40 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
41 SDValue Chain, uint64_t Offset) const;
42 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
43 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
44 const SDLoc &SL, SDValue Chain,
49 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
50 const SDLoc &SL, SDValue Chain,
52 SDValue getPreloadedValue(SelectionDAG &DAG,
57 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
59 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
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DAMDGPUISelLowering.h37 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
40 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
41 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
45 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
46 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
51 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
52 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
54 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
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/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.h449 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
519 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
520 SDValue &Offset,
527 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
534 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
539 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
546 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
551 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
554 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
555 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
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