Searched refs:SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT (Results 1 – 6 of 6) sorted by relevance
372 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in brw_instruction_name()1095 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in has_side_effects()
496 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT, enumerator
851 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT) in generate_urb_write()855 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT) in generate_urb_write()2345 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in generate_code()
915 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in instruction_desc()
230 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in is_send_from_grf()305 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in is_payload()975 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in size_read()1577 prev->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT) { in emit_gs_thread_end()6760 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: in get_lowered_simd_width()
2200 opcode = SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT; in emit_gs_control_data_bits()2963 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT : in nir_emit_tcs_intrinsic()