| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | GCNHazardRecognizer.cpp | 104 static bool isSendMsgTraceDataOrGDS(const SIInstrInfo &TII, in isSendMsgTraceDataOrGDS()
136 static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr) { in getHWReg()
152 if (SIInstrInfo::isSMRD(*MI) && checkSMRDHazards(MI) > 0) in getHazardType()
156 if ((SIInstrInfo::isVMEM(*MI) || in getHazardType()
157 SIInstrInfo::isFLAT(*MI)) in getHazardType()
170 if (SIInstrInfo::isVALU(*MI) && checkVALUHazards(MI) > 0) in getHazardType()
173 if (SIInstrInfo::isDPP(*MI) && checkDPPHazards(MI) > 0) in getHazardType()
200 if (SIInstrInfo::isMAI(*MI) && checkMAIHazards(MI) > 0) in getHazardType()
203 if ((SIInstrInfo::isVMEM(*MI) || in getHazardType()
204 SIInstrInfo::isFLAT(*MI) || in getHazardType()
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| D | SIInsertHardClauses.cpp | 68 if (SIInstrInfo::isVMEM(MI) || SIInstrInfo::isSegmentSpecificFLAT(MI)) in getHardClauseType()
70 if (SIInstrInfo::isFLAT(MI)) in getHardClauseType()
73 if (SIInstrInfo::isSMRD(MI)) in getHardClauseType()
112 bool emitClause(const ClauseInfo &CI, const SIInstrInfo *SII) { in emitClause()
138 const SIInstrInfo *SII = ST.getInstrInfo(); in runOnMachineFunction()
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| D | SIModeRegister.cpp | 148 void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII);
150 void processBlockPhase2(MachineBasicBlock &MBB, const SIInstrInfo *TII);
152 void processBlockPhase3(MachineBasicBlock &MBB, const SIInstrInfo *TII);
154 Status getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII);
157 const SIInstrInfo *TII, Status InstrMode);
175 const SIInstrInfo *TII) { in getInstructionMode()
197 const SIInstrInfo *TII, Status InstrMode) { in insertSetreg()
233 const SIInstrInfo *TII) { in processBlockPhase1()
335 const SIInstrInfo *TII) { in processBlockPhase2()
403 const SIInstrInfo *TII) { in processBlockPhase3()
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| D | SIInstrInfo.cpp | 95 SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST) in SIInstrInfo() function in SIInstrInfo
139 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI, in isReallyTriviallyReMaterializable()
157 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, in areLoadsFromSameBasePtr()
272 bool SIInstrInfo::getMemOperandsWithOffsetWidth( in getMemOperandsWithOffsetWidth()
472 bool SIInstrInfo::shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1, in shouldClusterMemOps()
511 bool SIInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, in shouldScheduleLoadsNear()
523 static void reportIllegalCopy(const SIInstrInfo *TII, MachineBasicBlock &MBB, in reportIllegalCopy()
539 static void indirectCopyToAGPR(const SIInstrInfo &TII, in indirectCopyToAGPR()
640 static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB, in expandSGPRCopy()
688 void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, in copyPhysReg()
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| D | AMDGPUExportClustering.cpp | 30 return SIInstrInfo::isEXP(*SU.getInstr()); in isExport()
33 static bool isPositionExport(const SIInstrInfo *TII, SUnit *SU) { in isPositionExport()
39 static void sortChain(const SIInstrInfo *TII, SmallVector<SUnit *, 8> &Chain, in sortChain()
109 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(DAG->TII); in apply()
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| D | AMDGPUMCInstLower.cpp | 83 case SIInstrInfo::MO_GOTPCREL: in getVariantKind()
85 case SIInstrInfo::MO_GOTPCREL32_LO: in getVariantKind()
87 case SIInstrInfo::MO_GOTPCREL32_HI: in getVariantKind()
89 case SIInstrInfo::MO_REL32_LO: in getVariantKind()
91 case SIInstrInfo::MO_REL32_HI: in getVariantKind()
93 case SIInstrInfo::MO_ABS32_LO: in getVariantKind()
95 case SIInstrInfo::MO_ABS32_HI: in getVariantKind()
119 if (MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_FORWARD) in getLongBranchBlockExpr()
122 assert(MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_BACKWARD); in getLongBranchBlockExpr()
178 const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo()); in lower()
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| D | AMDGPUMacroFusion.cpp | 32 const SIInstrInfo &TII = static_cast<const SIInstrInfo&>(TII_); in shouldScheduleAdjacent()
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| D | SIShrinkInstructions.cpp | 71 static bool foldImmediates(MachineInstr &MI, const SIInstrInfo *TII, in foldImmediates()
124 static bool isKImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) { in isKImmOperand()
130 static bool isKUImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) { in isKUImmOperand()
136 static bool isKImmOrKUImmOperand(const SIInstrInfo *TII, in isKImmOrKUImmOperand()
154 static bool isReverseInlineImm(const SIInstrInfo *TII, in isReverseInlineImm()
178 static void shrinkScalarCompare(const SIInstrInfo *TII, MachineInstr &MI) { in shrinkScalarCompare()
229 const SIInstrInfo *TII = ST.getInstrInfo(); in shrinkMIMG()
318 const SIInstrInfo *TII, in shrinkScalarLogicOp()
441 const SIInstrInfo *TII) { in dropInstructionKeepingImpDefs()
476 const SIInstrInfo *TII) { in matchSwap()
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| D | SIPeepholeSDWA.cpp | 75 const SIInstrInfo *TII;
121 virtual MachineInstr *potentialToConvert(const SIInstrInfo *TII) = 0;
122 virtual bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) = 0;
154 MachineInstr *potentialToConvert(const SIInstrInfo *TII) override;
155 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
162 uint64_t getSrcMods(const SIInstrInfo *TII,
181 MachineInstr *potentialToConvert(const SIInstrInfo *TII) override;
182 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
202 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
330 uint64_t SDWASrcOperand::getSrcMods(const SIInstrInfo *TII, in getSrcMods()
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| D | SIRegisterInfo.cpp | 395 assert(SIInstrInfo::isMUBUF(*MI) || SIInstrInfo::isFLATScratch(*MI)); in getScratchInstrOffset()
404 if (!SIInstrInfo::isMUBUF(*MI) && !SIInstrInfo::isFLATScratch(*MI)) in getFrameIndexInstrOffset()
422 if (SIInstrInfo::isMUBUF(*MI)) in needsFrameBaseReg()
423 return !SIInstrInfo::isLegalMUBUFImmOffset(FullOffset); in needsFrameBaseReg()
425 const SIInstrInfo *TII = ST.getInstrInfo(); in needsFrameBaseReg()
440 const SIInstrInfo *TII = ST.getInstrInfo(); in materializeFrameBaseRegister()
477 const SIInstrInfo *TII = ST.getInstrInfo(); in resolveFrameIndex()
521 assert(SIInstrInfo::isLegalMUBUFImmOffset(NewOffset) && in resolveFrameIndex()
531 if (!SIInstrInfo::isMUBUF(*MI) && !!SIInstrInfo::isFLATScratch(*MI)) in isFrameOffsetLegal()
536 if (SIInstrInfo::isMUBUF(*MI)) in isFrameOffsetLegal()
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| D | GCNHazardRecognizer.h | 29 class SIInstrInfo; variable
48 const SIInstrInfo &TII;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNHazardRecognizer.cpp | 93 static bool isSendMsgTraceDataOrGDS(const SIInstrInfo &TII, in isSendMsgTraceDataOrGDS()
125 static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr) { in getHWReg()
137 if (SIInstrInfo::isSMRD(*MI) && checkSMRDHazards(MI) > 0) in getHazardType()
141 if ((SIInstrInfo::isVMEM(*MI) || in getHazardType()
142 SIInstrInfo::isFLAT(*MI)) in getHazardType()
155 if (SIInstrInfo::isVALU(*MI) && checkVALUHazards(MI) > 0) in getHazardType()
158 if (SIInstrInfo::isDPP(*MI) && checkDPPHazards(MI) > 0) in getHazardType()
185 if (SIInstrInfo::isMAI(*MI) && checkMAIHazards(MI) > 0) in getHazardType()
200 static void insertNoopInBundle(MachineInstr *MI, const SIInstrInfo &TII) { in insertNoopInBundle()
251 if (SIInstrInfo::isSMRD(*MI)) in PreEmitNoopsCommon()
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| D | SIModeRegister.cpp | 144 void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII);
146 void processBlockPhase2(MachineBasicBlock &MBB, const SIInstrInfo *TII);
148 void processBlockPhase3(MachineBasicBlock &MBB, const SIInstrInfo *TII);
150 Status getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII);
153 const SIInstrInfo *TII, Status InstrMode);
171 const SIInstrInfo *TII) { in getInstructionMode()
193 const SIInstrInfo *TII, Status InstrMode) { in insertSetreg()
228 const SIInstrInfo *TII) { in processBlockPhase1()
327 const SIInstrInfo *TII) { in processBlockPhase2()
363 const SIInstrInfo *TII) { in processBlockPhase3()
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| D | SIInstrInfo.cpp | 86 SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST) in SIInstrInfo() function in SIInstrInfo
130 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI, in isReallyTriviallyReMaterializable()
146 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, in areLoadsFromSameBasePtr()
261 bool SIInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, in getMemOperandWithOffset()
436 bool SIInstrInfo::shouldClusterMemOps(const MachineOperand &BaseOp1, in shouldClusterMemOps()
504 bool SIInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, in shouldScheduleLoadsNear()
516 static void reportIllegalCopy(const SIInstrInfo *TII, MachineBasicBlock &MBB, in reportIllegalCopy()
531 void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, in copyPhysReg()
740 int SIInstrInfo::commuteOpcode(unsigned Opcode) const { in commuteOpcode()
758 void SIInstrInfo::materializeImmediate(MachineBasicBlock &MBB, in materializeImmediate()
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| D | AMDGPUMCInstLower.cpp | 83 case SIInstrInfo::MO_GOTPCREL: in getVariantKind()
85 case SIInstrInfo::MO_GOTPCREL32_LO: in getVariantKind()
87 case SIInstrInfo::MO_GOTPCREL32_HI: in getVariantKind()
89 case SIInstrInfo::MO_REL32_LO: in getVariantKind()
91 case SIInstrInfo::MO_REL32_HI: in getVariantKind()
93 case SIInstrInfo::MO_ABS32_LO: in getVariantKind()
95 case SIInstrInfo::MO_ABS32_HI: in getVariantKind()
119 if (MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_FORWARD) in getLongBranchBlockExpr()
122 assert(MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_BACKWARD); in getLongBranchBlockExpr()
178 const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo()); in lower()
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| D | SIFrameLowering.h | 16 class SIInstrInfo; variable
64 const SIInstrInfo *TII,
70 const GCNSubtarget &ST, const SIInstrInfo *TII, const SIRegisterInfo *TRI,
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| D | AMDGPUMacroFusion.cpp | 32 const SIInstrInfo &TII = static_cast<const SIInstrInfo&>(TII_); in shouldScheduleAdjacent()
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| D | SIShrinkInstructions.cpp | 71 static bool foldImmediates(MachineInstr &MI, const SIInstrInfo *TII, in foldImmediates()
128 static bool isKImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) { in isKImmOperand()
134 static bool isKUImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) { in isKUImmOperand()
140 static bool isKImmOrKUImmOperand(const SIInstrInfo *TII, in isKImmOrKUImmOperand()
158 static bool isReverseInlineImm(const SIInstrInfo *TII, in isReverseInlineImm()
182 static void shrinkScalarCompare(const SIInstrInfo *TII, MachineInstr &MI) { in shrinkScalarCompare()
228 const SIInstrInfo *TII = ST.getInstrInfo(); in shrinkMIMG()
317 const SIInstrInfo *TII, in shrinkScalarLogicOp()
456 const SIInstrInfo *TII) { in matchSwap()
555 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
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| D | SIPeepholeSDWA.cpp | 75 const SIInstrInfo *TII;
121 virtual MachineInstr *potentialToConvert(const SIInstrInfo *TII) = 0;
122 virtual bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) = 0;
154 MachineInstr *potentialToConvert(const SIInstrInfo *TII) override;
155 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
162 uint64_t getSrcMods(const SIInstrInfo *TII,
181 MachineInstr *potentialToConvert(const SIInstrInfo *TII) override;
182 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
202 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
330 uint64_t SDWASrcOperand::getSrcMods(const SIInstrInfo *TII, in getSrcMods()
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| D | SIOptimizeExecMasking.cpp | 181 static bool removeTerminatorBit(const SIInstrInfo &TII, MachineInstr &MI) { in removeTerminatorBit()
224 const SIInstrInfo &TII, in fixTerminators()
239 const SIInstrInfo &TII, in findExecCopy()
274 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
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| D | GCNHazardRecognizer.h | 29 class SIInstrInfo; variable
48 const SIInstrInfo &TII;
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| D | SIFormMemoryClauses.cpp | 101 return SIInstrInfo::isFLAT(MI) || SIInstrInfo::isVMEM(MI); in isVMEMClauseInst()
105 return SIInstrInfo::isSMRD(MI); in isSMEMClauseInst()
313 const SIInstrInfo *TII = ST->getInstrInfo(); in runOnMachineFunction()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | GCNHazardRecognizer.cpp | 45 if (SIInstrInfo::isSMRD(*MI) && checkSMRDHazards(MI) > 0) in getHazardType()
48 if (SIInstrInfo::isVMEM(*MI) && checkVMEMHazards(MI) > 0) in getHazardType()
51 if (SIInstrInfo::isDPP(*MI) && checkDPPHazards(MI) > 0) in getHazardType()
62 if (SIInstrInfo::isSMRD(*MI)) in PreEmitNoops()
65 if (SIInstrInfo::isVMEM(*MI)) in PreEmitNoops()
68 if (SIInstrInfo::isDPP(*MI)) in PreEmitNoops()
85 const SIInstrInfo *TII = ST.getInstrInfo(); in AdvanceCycle()
164 if (!MI || !SIInstrInfo::isSMRD(*MI)) in checkSMEMSoftClauseHazards()
199 const SIInstrInfo *TII = ST.getInstrInfo(); in checkSMRDHazards()
224 const SIInstrInfo *TII = ST.getInstrInfo(); in checkVMEMHazards()
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| D | SIInstrInfo.cpp | 31 SIInstrInfo::SIInstrInfo(const SISubtarget &ST) in SIInstrInfo() function in SIInstrInfo
78 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI, in isReallyTriviallyReMaterializable()
93 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, in areLoadsFromSameBasePtr()
205 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, in getMemOpBaseRegImmOfs()
299 bool SIInstrInfo::shouldClusterMemOps(MachineInstr &FirstLdSt, in shouldClusterMemOps()
341 void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, in copyPhysReg()
502 int SIInstrInfo::commuteOpcode(const MachineInstr &MI) const { in commuteOpcode()
522 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const { in getMovOpcode()
570 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, in storeRegToStackSlot()
669 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, in loadRegFromStackSlot()
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| D | SIShrinkInstructions.cpp | 80 static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII, in canShrink()
129 static void foldImmediates(MachineInstr &MI, const SIInstrInfo *TII, in foldImmediates()
193 static bool isKImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) { in isKImmOperand()
203 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
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