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/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/
Dsimdintrin.h31 typedef SIMD256 SIMD; typedef
39 #define _simd_load_ps SIMD::load_ps
40 #define _simd_load1_ps SIMD::broadcast_ss
41 #define _simd_loadu_ps SIMD::loadu_ps
42 #define _simd_setzero_ps SIMD::setzero_ps
43 #define _simd_set1_ps SIMD::set1_ps
44 #define _simd_blend_ps(a, b, i) SIMD::blend_ps<i>(a, b)
45 #define _simd_blend_epi32(a, b, i) SIMD::blend_epi32<i>(a, b)
46 #define _simd_blendv_ps SIMD::blendv_ps
47 #define _simd_store_ps SIMD::store_ps
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/external/swiftshader/src/Pipeline/
DSpirvShaderImage.cpp76 sw::SIMD::Float sRGBtoLinear(sw::SIMD::Float c) in sRGBtoLinear()
78 sw::SIMD::Float lc = c * sw::SIMD::Float(1.0f / 12.92f); in sRGBtoLinear()
79 …sw::SIMD::Float ec = sw::power((c + sw::SIMD::Float(0.055f)) * sw::SIMD::Float(1.0f / 1.055f), sw:… in sRGBtoLinear()
81 sw::SIMD::Int linear = CmpLT(c, sw::SIMD::Float(0.04045f)); in sRGBtoLinear()
83 …return rr::As<sw::SIMD::Float>((linear & rr::As<sw::SIMD::Int>(lc)) | (~linear & rr::As<sw::SIMD::… in sRGBtoLinear()
132 Array<SIMD::Float> out(4); in EmitImageSample()
147 void SpirvShader::EmitImageSampleUnconditional(Array<SIMD::Float> &out, ImageInstruction instructio… in EmitImageSampleUnconditional()
241 Array<SIMD::Float> in(16); // Maximum 16 input parameter components. in EmitImageSampleUnconditional()
304 in[i] = As<SIMD::Float>(SIMD::Int(0)); in EmitImageSampleUnconditional()
315 in[i] = As<SIMD::Float>(offsetValue.Int(j)); // Integer values, but transfered as float. in EmitImageSampleUnconditional()
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DSpirvShaderGLSLstd450.cpp27 sw::SIMD::Float Interpolate(const sw::SIMD::Float &x, const sw::SIMD::Float &y, const sw::SIMD::Flo… in Interpolate()
28 … const sw::SIMD::Float &A, const sw::SIMD::Float &B, const sw::SIMD::Float &C, in Interpolate()
31 sw::SIMD::Float interpolant = C; in Interpolate()
158 …dst.move(i, x + ((SIMD::Float(CmpLT(x, src.Float(i)) & SIMD::Int(1)) * SIMD::Float(2.0f)) - SIMD::… in EmitExtGLSLstd450()
159 …SIMD::Float(CmpEQ(Frac(src.Float(i)), SIMD::Float(0.5f)) & SIMD::Int(1)) * SIMD::Float(Int4(x) & S… in EmitExtGLSLstd450()
229 dst.move(i, CmpNLT(x.Float(i), edge.Float(i)) & As<SIMD::Int>(SIMD::Float(1.0f))); in EmitExtGLSLstd450()
242 SIMD::Float(0.0f)), in EmitExtGLSLstd450()
243 SIMD::Float(1.0f)); in EmitExtGLSLstd450()
297 …auto neg = As<SIMD::Int>(CmpLT(src.Float(i), SIMD::Float(-0.0f))) & As<SIMD::Int>(SIMD::Float(-1.0… in EmitExtGLSLstd450()
298 …auto pos = As<SIMD::Int>(CmpNLE(src.Float(i), SIMD::Float(+0.0f))) & As<SIMD::Int>(SIMD::Float(1.0… in EmitExtGLSLstd450()
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DSpirvShaderGroup.cpp41 …auto mask = As<SIMD::UInt>(state->activeLaneMask()); // Considers helper invocations active. See … in BinaryOperation()
43 SIMD::UInt v_uint = (value.UInt(i) & mask) | (As<SIMD::UInt>(identity) & ~mask); in BinaryOperation()
81 …static_assert(SIMD::Width == 4, "EmitGroupNonUniform makes many assumptions that the SIMD vector w… in EmitGroupNonUniform()
96 …SIMD::Int active = state->activeLaneMask(); // Considers helper invocations active. See b/1511370… in EmitGroupNonUniform()
99 auto v0111 = SIMD::Int(0, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); in EmitGroupNonUniform()
108 …dst.move(0, AndAll(predicate.UInt(0) | ~As<SIMD::UInt>(state->activeLaneMask()))); // Considers h… in EmitGroupNonUniform()
115 …dst.move(0, OrAll(predicate.UInt(0) & As<SIMD::UInt>(state->activeLaneMask()))); // Considers hel… in EmitGroupNonUniform()
122 auto res = SIMD::UInt(0xffffffff); in EmitGroupNonUniform()
123 …SIMD::UInt active = As<SIMD::UInt>(state->activeLaneMask()); // Considers helper invocations acti… in EmitGroupNonUniform()
124 SIMD::UInt inactive = ~active; in EmitGroupNonUniform()
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DShaderCore.hpp90 namespace SIMD { namespace
103 Pointer(rr::Pointer<Byte> base, rr::Int limit, SIMD::Int offset);
104 Pointer(rr::Pointer<Byte> base, unsigned int limit, SIMD::Int offset);
109 Pointer operator+(SIMD::Int i);
110 Pointer operator*(SIMD::Int i);
118 SIMD::Int offsets() const;
120 SIMD::Int isInBounds(unsigned int accessSize, OutOfBoundsBehavior robustness) const;
158 SIMD::Int dynamicOffsets; // If hasDynamicOffsets is false, all dynamicOffsets are zero.
159 std::array<int32_t, SIMD::Width> staticOffsets;
223 sw::SIMD::UInt halfToFloatBits(sw::SIMD::UInt halfBits);
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DShaderCore.cpp561 SIMD::UInt halfToFloatBits(SIMD::UInt halfBits) in halfToFloatBits()
563 auto magic = SIMD::UInt(126 << 23); in halfToFloatBits()
565 auto sign16 = halfBits & SIMD::UInt(0x8000); in halfToFloatBits()
566 auto man16 = halfBits & SIMD::UInt(0x03FF); in halfToFloatBits()
567 auto exp16 = halfBits & SIMD::UInt(0x7C00); in halfToFloatBits()
569 auto isDnormOrZero = CmpEQ(exp16, SIMD::UInt(0)); in halfToFloatBits()
570 auto isInfOrNaN = CmpEQ(exp16, SIMD::UInt(0x7C00)); in halfToFloatBits()
574 auto exp32 = (exp16 + SIMD::UInt(0x1C000)) << 13; in halfToFloatBits()
575 auto norm32 = (man32 | exp32) | (isInfOrNaN & SIMD::UInt(0x7F800000)); in halfToFloatBits()
577 auto denorm32 = As<SIMD::UInt>(As<SIMD::Float>(magic + man16) - As<SIMD::Float>(magic)); in halfToFloatBits()
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DSpirvShaderArithmetic.cpp48 SIMD::Float v = lhs.Float(i) * rhs.Float(0); in EmitMatrixTimesVector()
68 SIMD::Float v = lhs.Float(0) * rhs.Float(i * lhs.componentCount); in EmitVectorTimesMatrix()
94 SIMD::Float v = SIMD::Float(0); in EmitMatrixTimesMatrix()
166 auto one = SIMD::UInt(1); in EmitUnaryOp()
177 auto one = SIMD::UInt(1); in EmitUnaryOp()
179 SIMD::UInt out = (v >> offset) & Bitmask32(count); in EmitUnaryOp()
195 SIMD::UInt v = src.UInt(i); in EmitUnaryOp()
196 v = ((v >> 1) & SIMD::UInt(0x55555555)) | ((v & SIMD::UInt(0x55555555)) << 1); in EmitUnaryOp()
197 v = ((v >> 2) & SIMD::UInt(0x33333333)) | ((v & SIMD::UInt(0x33333333)) << 2); in EmitUnaryOp()
198 v = ((v >> 4) & SIMD::UInt(0x0F0F0F0F)) | ((v & SIMD::UInt(0x0F0F0F0F)) << 4); in EmitUnaryOp()
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DComputeProgram.cpp73 …:BuiltInNumWorkgroups, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in setWorkgroupBuiltins()
77 As<SIMD::Float>(SIMD::Int(Extract(routine->numWorkgroups, component))); in setWorkgroupBuiltins()
81 …v::BuiltInWorkgroupId, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in setWorkgroupBuiltins()
85 As<SIMD::Float>(SIMD::Int(workgroupID[component])); in setWorkgroupBuiltins()
89 …:BuiltInWorkgroupSize, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in setWorkgroupBuiltins()
93 As<SIMD::Float>(SIMD::Int(Extract(routine->workgroupSize, component))); in setWorkgroupBuiltins()
97 …::BuiltInNumSubgroups, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in setWorkgroupBuiltins()
99 value[builtin.FirstComponent] = As<SIMD::Float>(SIMD::Int(routine->subgroupsPerWorkgroup)); in setWorkgroupBuiltins()
102 …::BuiltInSubgroupSize, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in setWorkgroupBuiltins()
104 value[builtin.FirstComponent] = As<SIMD::Float>(SIMD::Int(routine->invocationsPerSubgroup)); in setWorkgroupBuiltins()
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DVertexProgram.cpp42 …spv::BuiltInViewIndex, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in VertexProgram()
44 value[builtin.FirstComponent] = As<SIMD::Float>(SIMD::Int(routine.viewID)); in VertexProgram()
47 …:BuiltInInstanceIndex, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in VertexProgram()
50 value[builtin.FirstComponent] = As<SIMD::Float>(SIMD::Int(routine.instanceID)); in VertexProgram()
53 …::BuiltInSubgroupSize, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in VertexProgram()
55 value[builtin.FirstComponent] = As<SIMD::Float>(SIMD::Int(SIMD::Width)); in VertexProgram()
70 routine.vertexIndex = *Pointer<SIMD::Int>(As<Pointer<SIMD::Int>>(batch)) + in program()
71 SIMD::Int(*Pointer<Int>(data + OFFSET(DrawData, baseVertex))); in program()
78 As<SIMD::Float>(routine.vertexIndex); in program()
81 auto activeLaneMask = SIMD::Int(0xFFFFFFFF); in program()
DPixelProgram.cpp89 routine.fragCoord[0] = SIMD::Float(Float(x)) + SIMD::Float(x0, x1, x0, x1); in setBuiltins()
90 routine.fragCoord[1] = SIMD::Float(Float(y)) + SIMD::Float(y0, y0, y1, y1); in setBuiltins()
94 routine.invocationsPerSubgroup = SIMD::Width; in setBuiltins()
96 routine.windowSpacePosition[0] = x + SIMD::Int(0, 1, 0, 1); in setBuiltins()
97 routine.windowSpacePosition[1] = y + SIMD::Int(0, 0, 1, 1); in setBuiltins()
102 …SIMD::Float pointSizeInv = SIMD::Float(*Pointer<Float>(primitive + OFFSET(Primitive, pointSizeInv)… in setBuiltins()
103 …routine.pointCoord[0] = SIMD::Float(0.5f) + pointSizeInv * (((SIMD::Float(Float(x)) + SIMD::Float(… in setBuiltins()
104 …routine.pointCoord[1] = SIMD::Float(0.5f) + pointSizeInv * (((SIMD::Float(Float(y)) + SIMD::Float(… in setBuiltins()
106 …spv::BuiltInViewIndex, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in setBuiltins()
108 value[builtin.FirstComponent] = As<SIMD::Float>(SIMD::Int(routine.viewID)); in setBuiltins()
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DSpirvShader.hpp95 …void move(uint32_t i, RValue<SIMD::Float> &&scalar) { emplace(i, scalar.value(), TypeHint::Float);… in move()
96 void move(uint32_t i, RValue<SIMD::Int> &&scalar) { emplace(i, scalar.value(), TypeHint::Int); } in move()
97 void move(uint32_t i, RValue<SIMD::UInt> &&scalar) { emplace(i, scalar.value(), TypeHint::UInt); } in move()
99 …void move(uint32_t i, const RValue<SIMD::Float> &scalar) { emplace(i, scalar.value(), TypeHint::Fl… in move()
100 …void move(uint32_t i, const RValue<SIMD::Int> &scalar) { emplace(i, scalar.value(), TypeHint::Int)… in move()
101 …void move(uint32_t i, const RValue<SIMD::UInt> &scalar) { emplace(i, scalar.value(), TypeHint::UIn… in move()
104 RValue<SIMD::Float> Float(uint32_t i) const in Float()
108 return As<SIMD::Float>(scalar[i]); // TODO(b/128539387): RValue<SIMD::Float>(scalar) in Float()
111 RValue<SIMD::Int> Int(uint32_t i) const in Int()
115 return As<SIMD::Int>(scalar[i]); // TODO(b/128539387): RValue<SIMD::Int>(scalar) in Int()
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DSpirvShaderSampling.cpp99 …rr::Function<Void(Pointer<Byte>, Pointer<SIMD::Float>, Pointer<SIMD::Float>, Pointer<Byte>)> funct… in emitSamplerRoutine()
102 Pointer<SIMD::Float> in = function.Arg<1>(); in emitSamplerRoutine()
103 Pointer<SIMD::Float> out = function.Arg<2>(); in emitSamplerRoutine()
106 SIMD::Float uvwa[4]; in emitSamplerRoutine()
107 SIMD::Float dRef; in emitSamplerRoutine()
108 …SIMD::Float lodOrBias; // Explicit level-of-detail, or bias added to the implicit level-of-detail… in emitSamplerRoutine()
112 SIMD::Int sampleId; in emitSamplerRoutine()
147 offset[j] = As<SIMD::Int>(in[i]); in emitSamplerRoutine()
152 sampleId = As<SIMD::Int>(in[i]); in emitSamplerRoutine()
163 For(Int i = 0, i < SIMD::Width, i++) in emitSamplerRoutine()
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DSpirvShaderDebug.hpp79 return PrintValue::Ty<sw::SIMD::Float>::fmt(v.Float(i)); in fmt()
81 return PrintValue::Ty<sw::SIMD::Int>::fmt(v.Int(i)); in fmt()
83 return PrintValue::Ty<sw::SIMD::UInt>::fmt(v.UInt(i)); in fmt()
93 return PrintValue::Ty<sw::SIMD::Float>::val(v.Float(i)); in val()
95 return PrintValue::Ty<sw::SIMD::Int>::val(v.Int(i)); in val()
97 return PrintValue::Ty<sw::SIMD::UInt>::val(v.UInt(i)); in val()
136 …intValue::Ty<sw::Intermediate>::fmt(*v.intermediate) : PrintValue::Ty<sw::SIMD::UInt>::fmt(v.UInt(… in fmt()
141 …intValue::Ty<sw::Intermediate>::val(*v.intermediate) : PrintValue::Ty<sw::SIMD::UInt>::val(v.UInt(… in val()
DSpirvShaderMemory.cpp64 dst.move(el.index, p.Load<SIMD::Float>(robustness, state->activeLaneMask(), atomic, memoryOrder)); in EmitLoad()
105 SIMD::Int mask = state->activeLaneMask(); in Store()
136 auto size = elementTy.componentCount * static_cast<uint32_t>(sizeof(float)) * SIMD::Width; in EmitVariable()
137 state->createPointer(resultId, SIMD::Pointer(base, size)); in EmitVariable()
145 state->createPointer(resultId, SIMD::Pointer(base, size, workgroupMemory.offsetOf(resultId))); in EmitVariable()
163 auto size = elementTy.componentCount * static_cast<uint32_t>(sizeof(float)) * SIMD::Width; in EmitVariable()
164 state->createPointer(resultId, SIMD::Pointer(base, size)); in EmitVariable()
177 state->createPointer(resultId, SIMD::Pointer(binding, size)); in EmitVariable()
191 state->createPointer(resultId, SIMD::Pointer(routine->descriptorSets[d.DescriptorSet], size)); in EmitVariable()
195 state->createPointer(resultId, SIMD::Pointer(nullptr, 0)); in EmitVariable()
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DSpirvShader.cpp1145 SIMD::Pointer SpirvShader::WalkExplicitLayoutAccessChain(Object::ID baseId, uint32_t numIndexes, ui… in WalkExplicitLayoutAccessChain()
1210 ptr += SIMD::Int(d.ArrayStride) * state->getIntermediate(indexIds[i]).Int(0); in WalkExplicitLayoutAccessChain()
1228 ptr += SIMD::Int(columnStride) * state->getIntermediate(indexIds[i]).Int(0); in WalkExplicitLayoutAccessChain()
1243 ptr += SIMD::Int(elemStride) * state->getIntermediate(indexIds[i]).Int(0); in WalkExplicitLayoutAccessChain()
1257 SIMD::Pointer SpirvShader::WalkAccessChain(Object::ID baseId, uint32_t numIndexes, uint32_t const *… in WalkAccessChain()
1322 ptr += SIMD::Int(stride) * state->getIntermediate(indexIds[i]).Int(0); in WalkAccessChain()
1633 void SpirvShader::emit(SpirvRoutine *routine, RValue<SIMD::Int> const &activeLaneMask, RValue<SIMD:… in emit()
2181 dst.move(i, RValue<SIMD::Float>(0.0f)); in EmitVectorShuffle()
2205 SIMD::UInt v = SIMD::UInt(0); in EmitVectorExtractDynamic()
2209 v |= CmpEQ(index.UInt(0), SIMD::UInt(i)) & src.UInt(i); in EmitVectorExtractDynamic()
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DSpirvShaderControlFlow.cpp198 void SpirvShader::EmitState::addOutputActiveLaneMaskEdge(Block::ID to, RValue<SIMD::Int> mask) in addOutputActiveLaneMaskEdge()
203 void SpirvShader::EmitState::addActiveLaneMaskEdge(Block::ID from, Block::ID to, RValue<SIMD::Int> … in addActiveLaneMaskEdge()
219 RValue<SIMD::Int> SpirvShader::GetActiveLaneMaskEdge(EmitState *state, Block::ID from, Block::ID to… in GetActiveLaneMaskEdge()
301 SIMD::Int activeLaneMask(0); in EmitNonLoop()
367 SIMD::Int loopActiveLaneMask = SIMD::Int(0); in EmitLoop()
375 std::unordered_map<Block::ID, SIMD::Int> mergeActiveLaneMasks; in EmitLoop()
378 mergeActiveLaneMasks.emplace(in, SIMD::Int(0)); in EmitLoop()
419 loopActiveLaneMask = SIMD::Int(0); in EmitLoop()
540 SIMD::Int defaultLaneMask = state->activeLaneMask(); in EmitSwitch()
543 std::vector<RValue<SIMD::Int>> caseLabelMatches; in EmitSwitch()
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/external/llvm-project/llvm/test/CodeGen/WebAssembly/
Dsimd-build-vector.ll2 …-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes=CHECK,SIMD-VM
13 ; SIMD-VM-NEXT: i64.const $push0=, 8589934593
14 ; SIMD-VM-NEXT: i64x2.splat $push1=, $pop0
15 ; SIMD-VM-NEXT: return $pop1
23 ; SIMD-VM-NEXT: i64.const $push0=, 8589934593
24 ; SIMD-VM-NEXT: i64x2.splat $push1=, $pop0
25 ; SIMD-VM-NEXT: return $pop1
33 ; SIMD-VM-NEXT: i64.const $push0=, 8589934593
34 ; SIMD-VM-NEXT: i64x2.splat $push1=, $pop0
35 ; SIMD-VM-NEXT: return $pop1
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/external/llvm-project/flang/docs/
DOpenMP-4.5-grammar.md61 2.8.1 simd -> SIMD [simd-clause[ [,] simd-clause]...]
71 2.8.1 end-simd -> END SIMD
73 2.8.2 declare-simd -> DECLARE SIMD [(proc-name)] [declare-simd-clause[ [,] declare-simd-clause]...]
81 2.8.3 do-simd -> DO SIMD [do-simd-clause[ [,] do-simd-clause]...]
85 2.8.3 end-do-simd -> END DO SIMD [nowait-clause]
119 2.9.3 taskloop-simd -> TASKLOOP SIMD [taskloop-simd-clause[ [,] taskloop-simd-clause]...]
123 2.9.3 end-taskloop-simd -> END TASKLOOP SIMD
196 2.10.9 distribute-simd -> DISTRIBUTE SIMD [distribute-simd-clause[ [,] distribute-simd-clause]...]
200 2.10.9 end-distribute-simd -> END DISTRIBUTE SIMD
210 …DISTRIBUTE PARALLEL DO SIMD [distribute-parallel-do-simd-clause[ [,] distribute-parallel-do-simd-c…
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/external/fec/
DREADME37 SIMD SUPPORT
39 This package automatically makes use of various SIMD (Single
48 Many of the SIMD versions run more than an order of
49 magnitude faster than their portable C versions. The available SIMD
51 version of each routine is automatically selected. If no SIMD
56 The SIMD-assisted versions generally produce the same results as the C
59 path metrics. On the other hand, the SIMD versions use the
67 AMD CPUs starting with the K6. SSE (SIMD Streaming Extensions) was
73 The latest IA-32 SIMD instruction set, SSE3 (also known as "Prescott
98 Add SIMD version override options
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/external/llvm-project/clang-tools-extra/docs/clang-tidy/checks/
Dportability-simd-intrinsics.rst6 Finds SIMD intrinsics calls and suggests ``std::experimental::simd`` (`P0214`_)
22 Many architectures provide SIMD operations (e.g. x86 SSE/AVX, Power AltiVec/VSX,
23 ARM NEON). It is common that SIMD code implementing the same algorithm, is
27 The C++ standard proposal `P0214`_ and its extensions cover many common SIMD
29 operations, the SIMD code can be simplified and pieces for different targets can
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrSIMD.td1 // WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-//
11 /// \brief WebAssembly SIMD operand code-gen constructs.
15 // TODO: Implement SIMD instructions.
/external/psimd/
DREADME.md1 # P(ortable) SIMD
2 Portable 128-bit SIMD intrinsics
/external/mesa3d/src/gallium/drivers/swr/rasterizer/core/
Dfrontend.cpp1115 simdscalari vViewportIdx = SIMD::setzero_si(); in GeometryShaderStage()
1116 simdscalari vRtIdx = SIMD::setzero_si(); in GeometryShaderStage()
1117 SIMD::Vec4 svgAttrib[4]; in GeometryShaderStage()
1128 SIMD::castps_si(svgAttrib[0][VERTEX_SGV_VAI_COMP]); in GeometryShaderStage()
1132 SIMD::max_epi32(vViewportIdx, SIMD::setzero_si()); in GeometryShaderStage()
1134 SIMD::set1_epi32(KNOB_NUM_VIEWPORTS_SCISSORS); in GeometryShaderStage()
1136 SIMD::cmplt_epi32(vViewportIdx, vNumViewports); in GeometryShaderStage()
1137 vViewportIdx = SIMD::and_si(vClearMask, vViewportIdx); in GeometryShaderStage()
1142 vRtIdx = SIMD::castps_si(svgAttrib[0][VERTEX_SGV_RTAI_COMP]); in GeometryShaderStage()
1595 simdscalari vViewportIdx = SIMD::setzero_si(); in TessellationStages()
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/external/oboe/samples/RhythmGame/third_party/glm/
DCMakeLists.txt34 source_group("SIMD Files" FILES ${SIMD_SOURCE})
35 source_group("SIMD Files" FILES ${SIMD_INLINE})
36 source_group("SIMD Files" FILES ${SIMD_HEADER})
/external/libjpeg-turbo/simd/x86_64/
Djsimdcpu.asm2 ; jsimdcpu.asm - SIMD instruction support check
8 ; x86 SIMD extension for IJG JPEG library
24 ; Check if the CPU supports SIMD instructions

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