Searched refs:SI_CONTEXT_WB_L2 (Results 1 – 6 of 6) sorted by relevance
1052 SI_CONTEXT_INV_L2 | SI_CONTEXT_WB_L2 | SI_CONTEXT_INV_L2_METADATA | in gfx10_emit_cache_flush()1094 } else if (flags & SI_CONTEXT_WB_L2) { in gfx10_emit_cache_flush()1229 SI_CONTEXT_INV_L2 | SI_CONTEXT_WB_L2 | SI_CONTEXT_INV_L2_METADATA | in si_emit_cache_flush()1373 flags &= ~(SI_CONTEXT_INV_L2 | SI_CONTEXT_WB_L2 | SI_CONTEXT_INV_VCACHE); in si_emit_cache_flush()1394 SI_CONTEXT_INV_L2 | SI_CONTEXT_WB_L2)))) { in si_emit_cache_flush()1408 if (flags & SI_CONTEXT_INV_L2 || (sctx->chip_class <= GFX7 && (flags & SI_CONTEXT_WB_L2))) { in si_emit_cache_flush()1421 if (flags & SI_CONTEXT_WB_L2) { in si_emit_cache_flush()1911 sctx->flags |= SI_CONTEXT_WB_L2; in si_multi_draw_vbo()1932 sctx->flags |= SI_CONTEXT_WB_L2; in si_multi_draw_vbo()1938 sctx->flags |= SI_CONTEXT_WB_L2; in si_multi_draw_vbo()
105 sctx->flags |= sctx->chip_class <= GFX8 ? SI_CONTEXT_WB_L2 : 0; in si_launch_grid_internal()268 sctx->flags |= cache_policy == L2_BYPASS ? SI_CONTEXT_WB_L2 : 0; in si_compute_do_clear_or_copy()
838 sctx->flags |= SI_CONTEXT_WB_L2; in si_launch_grid()
79 #define SI_CONTEXT_WB_L2 (1 << 7) macro
1259 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2; in radeonsi_screen_create_impl()
4911 sctx->flags |= SI_CONTEXT_WB_L2; in si_memory_barrier()4921 sctx->flags |= SI_CONTEXT_WB_L2; in si_memory_barrier()4926 sctx->flags |= SI_CONTEXT_WB_L2; in si_memory_barrier()