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Searched refs:SI_NUM_SHADER_BUFFERS (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state.h40 #define SI_NUM_SHADER_BUFFERS 32 macro
607 return SI_NUM_SHADER_BUFFERS + slot; in si_get_constbuf_slot()
613 return SI_NUM_SHADER_BUFFERS - 1 - slot; in si_get_shaderbuf_slot()
Dsi_shader_llvm_resources.c104 LLVMBuildAdd(ctx->ac.builder, index, LLVMConstInt(ctx->ac.i32, SI_NUM_SHADER_BUFFERS, 0), ""); in load_ubo()
121 index = LLVMBuildSub(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, SI_NUM_SHADER_BUFFERS - 1, 0), in load_ssbo()
Dsi_debug.c798 sctx->const_and_shader_buffers[processor].enabled_mask >> SI_NUM_SHADER_BUFFERS; in si_dump_descriptors()
800 u_bit_consecutive64(0, SI_NUM_SHADER_BUFFERS); in si_dump_descriptors()
802 for (int i = 0; i < SI_NUM_SHADER_BUFFERS; i++) { in si_dump_descriptors()
805 1llu << (SI_NUM_SHADER_BUFFERS - i - 1)) << i; in si_dump_descriptors()
Dsi_descriptors.c1008 i < SI_NUM_SHADER_BUFFERS ? buffers->priority : buffers->priority_constbuf); in si_buffer_resources_begin_new_cs()
1270 assert(start_slot + count <= SI_NUM_SHADER_BUFFERS); in si_set_shader_buffers()
1578 u_bit_consecutive64(SI_NUM_SHADER_BUFFERS, SI_NUM_CONST_BUFFERS), in si_rebind_buffer()
1586 u_bit_consecutive64(0, SI_NUM_SHADER_BUFFERS), buf, in si_rebind_buffer()
2547 unsigned num_buffer_slots = SI_NUM_SHADER_BUFFERS + SI_NUM_CONST_BUFFERS; in si_init_all_descriptors()
Dsi_get.c416 return SI_NUM_SHADER_BUFFERS; in si_get_shader_param()
/external/mesa3d/docs/relnotes/
D20.2.0.rst3729 - radeonsi: bump SI_NUM_SHADER_BUFFERS to 32