| /external/llvm/docs/ |
| D | AMDGPUUsage.rst | 63 SOP1 Instructions
65 All SOP1 instructions are supported.
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_opcodes.py | 35 SOP1 = 1 variable in Format
391 SOP1 = { variable
464 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOP1:
465 opcode(name, gfx7, gfx9, gfx10, Format.SOP1)
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| D | aco_validate.cpp | 237 check(instr->format == Format::SOP1 || in validate_ir()
319 if (instr->format == Format::SOP1 || instr->format == Format::SOP2) { in validate_ir()
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| D | aco_ir.h | 72 SOP1 = 1, enumerator
928 return format == Format::SOP1 || in isSALU()
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| D | aco_spill.cpp | 246 …if (instr->format != Format::VOP1 && instr->format != Format::SOP1 && instr->format != Format::PSE… in should_rematerialize()
273 …assert((instr->format == Format::VOP1 || instr->format == Format::SOP1 || instr->format == Format:… in do_reload()
280 } else if (instr->format == Format::SOP1) { in do_reload()
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| D | aco_insert_NOPs.cpp | 689 …nstruction> s_mov{create_instruction<SOP1_instruction>(aco_opcode::s_mov_b32, Format::SOP1, 1, 1)}; in handle_instruction_gfx10()
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| D | aco_assembler.cpp | 139 case Format::SOP1: { in emit_instruction()
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| D | aco_insert_exec_mask.cpp | 760 …instr.reset(create_instruction<SOP1_instruction>(bld.w64or32(Builder::s_mov), Format::SOP1, 1, 1)); in process_instructions()
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| D | aco_register_allocation.cpp | 2365 … mov.reset(create_instruction<SOP1_instruction>(aco_opcode::s_mov_b32, Format::SOP1, 1, 1)); in register_allocation()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 25 field bits<1> SOP1 = 0;
61 let TSFlags{5} = SOP1;
282 class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
289 let SOP1 = 1;
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| D | SIDefines.h | 22 SOP1 = 1 << 5, enumerator
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| D | SIInstrInfo.h | 208 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
212 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
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| D | SIInstrInfo.td | 718 SOP1 <outs, ins, "", pattern>,
725 SOP1 <outs, ins, asm, []>,
735 SOP1 <outs, ins, asm, []>,
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| D | SIInstructions.td | 87 // SOP1 Instructions
2421 // SOP1 Patterns
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 21 field bit SOP1 = 0;
142 let TSFlags{2} = SOP1;
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| D | SOPInstructions.td | 37 // SOP1 Instructions
48 let SOP1 = 1;
1324 // SOP1 Patterns
1432 // SOP1 - GFX10.
1460 // SOP1 - GFX6, GFX7.
1958 // SOP1 - GFX9.
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| D | SIDefines.h | 25 SOP1 = 1 << 2, enumerator
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| D | SIInstrInfo.h | 364 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
368 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
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| D | SIInstructions.td | 569 let SOP1 = 1;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 21 field bit SOP1 = 0;
134 let TSFlags{2} = SOP1;
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| D | SIDefines.h | 25 SOP1 = 1 << 2, enumerator
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| D | SOPInstructions.td | 37 // SOP1 Instructions
48 let SOP1 = 1;
1199 // SOP1 Patterns
1269 // SOP1 - GFX10.
1302 // SOP1 - GFX6, GFX7.
1660 // SOP1 - GFX9.
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| D | SIInstrInfo.h | 358 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
362 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
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| /external/llvm-project/llvm/docs/AMDGPU/ |
| D | AMDGPUAsmGFX7.rst | 442 SOP1 section in Instructions
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| /external/llvm-project/llvm/docs/ |
| D | AMDGPUUsage.rst | 8790 SOP1 subsubsection
8803 For full list of supported instructions, refer to "SOP1 Instructions" in ISA
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