| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVFrameLowering.cpp | 117 Register SPReg = getSPReg(STI); in emitPrologue() local
137 if (STI.isRegisterReservedByUser(SPReg)) in emitPrologue()
147 adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup); in emitPrologue()
181 adjustReg(MBB, MBBI, DL, FPReg, SPReg, in emitPrologue()
196 adjustReg(MBB, MBBI, DL, SPReg, SPReg, -SecondSPAdjustAmount, in emitPrologue()
218 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg) in emitPrologue()
219 .addReg(SPReg) in emitPrologue()
226 .addReg(SPReg) in emitPrologue()
228 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg) in emitPrologue()
238 .addReg(SPReg) in emitPrologue()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFrameLowering.cpp | 174 unsigned SPReg = WebAssembly::SP32; in emitPrologue() local
176 SPReg = MRI.createVirtualRegister(PtrRC); in emitPrologue()
180 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::GLOBAL_GET_I32), SPReg) in emitPrologue()
189 .addReg(SPReg); in emitPrologue()
198 .addReg(SPReg) in emitPrologue()
240 unsigned SPReg = 0; in emitEpilogue() local
243 SPReg = FI->getBasePointerVreg(); in emitEpilogue()
252 SPReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue()
253 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::ADD_I32), SPReg) in emitEpilogue()
257 SPReg = hasFP(MF) ? WebAssembly::FP32 : WebAssembly::SP32; in emitEpilogue()
[all …]
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| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFrameLowering.cpp | 229 unsigned SPReg = getSPReg(MF); in emitPrologue() local
231 SPReg = MRI.createVirtualRegister(PtrRC); in emitPrologue()
235 BuildMI(MBB, InsertPt, DL, TII->get(getOpcGlobGet(MF)), SPReg) in emitPrologue()
244 .addReg(SPReg); in emitPrologue()
252 .addReg(SPReg) in emitPrologue()
292 unsigned SPReg = 0; in emitEpilogue() local
296 SPReg = FI->getBasePointerVreg(); in emitEpilogue()
306 SPReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue()
307 BuildMI(MBB, InsertPt, DL, TII->get(getOpcAdd(MF)), SPReg) in emitEpilogue()
311 SPReg = SPFPReg; in emitEpilogue()
[all …]
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFrameLowering.cpp | 141 unsigned SPReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() local
151 StackSize ? SPReg : (unsigned)WebAssembly::SP32) in emitPrologue()
164 .addReg(SPReg) in emitPrologue()
195 unsigned SPReg = 0; in emitEpilogue() local
206 SPReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue()
207 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::ADD_I32), SPReg) in emitEpilogue()
211 SPReg = hasFP(MF) ? WebAssembly::FP32 : WebAssembly::SP32; in emitEpilogue()
214 writeSPToMemory(SPReg, MF, MBB, InsertAddr, InsertPt, DL); in emitEpilogue()
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 645 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1; in emitPrologue() local
792 .addReg(SPReg); in emitPrologue()
806 .addReg(SPReg); in emitPrologue()
811 .addReg(SPReg); in emitPrologue()
816 .addReg(SPReg); in emitPrologue()
823 .addReg(SPReg); in emitPrologue()
831 .addReg(SPReg); in emitPrologue()
844 .addReg(SPReg) in emitPrologue()
845 .addReg(SPReg); in emitPrologue()
870 .addReg(SPReg); in emitPrologue()
[all …]
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| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVFrameLowering.cpp | 321 Register SPReg = getSPReg(STI); in emitPrologue() local
380 if (STI.isRegisterReservedByUser(SPReg)) in emitPrologue()
392 adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup); in emitPrologue()
435 adjustReg(MBB, MBBI, DL, FPReg, SPReg, in emitPrologue()
451 adjustReg(MBB, MBBI, DL, SPReg, SPReg, -SecondSPAdjustAmount, in emitPrologue()
473 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg) in emitPrologue()
474 .addReg(SPReg) in emitPrologue()
481 .addReg(SPReg) in emitPrologue()
483 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg) in emitPrologue()
493 .addReg(SPReg) in emitPrologue()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 747 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; in emitPrologue() local
856 .addReg(SPReg); in emitPrologue()
885 .addReg(SPReg); in emitPrologue()
892 .addReg(SPReg); in emitPrologue()
899 .addReg(SPReg); in emitPrologue()
906 .addReg(SPReg); in emitPrologue()
913 .addReg(SPReg); in emitPrologue()
924 .addReg(SPReg) in emitPrologue()
925 .addReg(SPReg); in emitPrologue()
932 .addReg(SPReg) in emitPrologue()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 831 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; in emitPrologue() local
983 .addReg(SPReg); in emitPrologue()
1012 .addReg(SPReg); in emitPrologue()
1017 .addReg(SPReg); in emitPrologue()
1022 .addReg(SPReg); in emitPrologue()
1029 .addReg(SPReg); in emitPrologue()
1037 .addReg(SPReg); in emitPrologue()
1050 .addReg(SPReg) in emitPrologue()
1051 .addReg(SPReg); in emitPrologue()
1062 .addReg(SPReg) in emitPrologue()
[all …]
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| /external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 136 unsigned SPReg = MI.getOperand(0).getReg(); in sandboxLoadStoreStackChange() local
137 assert((Mips::SP == SPReg) && "Unexpected stack-pointer register."); in sandboxLoadStoreStackChange()
138 emitMask(SPReg, LoadStoreStackMaskReg, STI); in sandboxLoadStoreStackChange()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 128 unsigned SPReg = MI.getOperand(0).getReg(); in sandboxLoadStoreStackChange() local
129 assert((Mips::SP == SPReg) && "Unexpected stack-pointer register."); in sandboxLoadStoreStackChange()
130 emitMask(SPReg, LoadStoreStackMaskReg, STI); in sandboxLoadStoreStackChange()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 136 unsigned SPReg = MI.getOperand(0).getReg(); in sandboxLoadStoreStackChange() local
137 assert((Mips::SP == SPReg) && "Unexpected stack-pointer register."); in sandboxLoadStoreStackChange()
138 emitMask(SPReg, LoadStoreStackMaskReg, STI); in sandboxLoadStoreStackChange()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFrameLowering.cpp | 95 unsigned ScratchRsrcReg, unsigned SPReg, int FI) { in buildPrologSpill() argument
109 .addReg(SPReg) in buildPrologSpill()
130 .addReg(SPReg) in buildPrologSpill()
143 unsigned ScratchRsrcReg, unsigned SPReg, int FI) { in buildEpilogReload() argument
156 .addReg(SPReg) in buildEpilogReload()
177 .addReg(SPReg) in buildEpilogReload()
493 unsigned SPReg = MFI->getStackPtrOffsetReg(); in emitEntryFunctionPrologue() local
494 assert(SPReg != AMDGPU::SP_REG); in emitEntryFunctionPrologue()
522 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), SPReg) in emitEntryFunctionPrologue()
525 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), SPReg) in emitEntryFunctionPrologue()
[all …]
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIFrameLowering.cpp | 141 Register ScratchRsrcReg, Register SPReg, int FI) { in buildPrologSpill() argument
155 .addReg(SPReg) in buildPrologSpill()
167 .addReg(SPReg) in buildPrologSpill()
187 .addReg(SPReg) in buildPrologSpill()
209 .addReg(SPReg) in buildPrologSpill()
226 Register ScratchRsrcReg, Register SPReg, int FI) { in buildEpilogReload() argument
239 .addReg(SPReg) in buildEpilogReload()
251 .addReg(SPReg) in buildEpilogReload()
268 .addReg(SPReg) in buildEpilogReload()
289 .addReg(SPReg) in buildEpilogReload()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FrameLowering.h | 103 int FI, unsigned &SPReg) const;
105 int FI, unsigned &SPReg, int Adjustment) const;
|
| D | X86RetpolineThunks.cpp | 232 const unsigned SPReg = Is64Bit ? X86::RSP : X86::ESP; in insertRegReturnAddrClobber() local
233 addRegOffset(BuildMI(&MBB, DebugLoc(), TII->get(MovOpc)), SPReg, false, 0) in insertRegReturnAddrClobber()
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| D | X86CallLowering.cpp | 111 Register SPReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
112 MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister()); in getStackAddress()
118 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86IndirectThunks.cpp | 246 const Register SPReg = Is64Bit ? X86::RSP : X86::ESP; in populateThunk() local
247 addRegOffset(BuildMI(CallTarget, DebugLoc(), TII->get(MovOpc)), SPReg, false, in populateThunk()
|
| D | X86FrameLowering.h | 110 Register &SPReg) const;
112 Register &SPReg, int Adjustment) const;
|
| D | X86CallLowering.cpp | 110 auto SPReg = in getStackAddress() local
115 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
|
| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64CallLowering.cpp | 139 StackSize(0), SPReg(0) {} in OutgoingArgHandler()
155 if (!SPReg) in getStackAddress()
156 SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0); in getStackAddress()
160 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
229 Register SPReg; member
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 102 Register SPReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
103 MIRBuilder.buildCopy(SPReg, Register(ARM::SP)); in getStackAddress()
109 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 101 auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP)); in getStackAddress() local
105 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 294 Register SPReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
295 MIRBuilder.buildCopy(SPReg, Register(Mips::SP)); in getStackAddress()
302 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
|
| /external/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 1437 unsigned SPReg; in getPSPSlotOffsetFromSP() local
1438 int Offset = getFrameIndexReferencePreferSP(MF, Info.PSPSymFrameIdx, SPReg, in getPSPSlotOffsetFromSP()
1440 assert(Offset >= 0 && SPReg == TRI->getStackRegister()); in getPSPSlotOffsetFromSP()
2448 unsigned ScratchReg, SPReg, PReg, SPLimitOffset; in adjustForHiPEPrologue() local
2452 SPReg = X86::RSP; in adjustForHiPEPrologue()
2458 SPReg = X86::ESP; in adjustForHiPEPrologue()
2471 SPReg, false, -MaxStack); in adjustForHiPEPrologue()
2481 SPReg, false, -MaxStack); in adjustForHiPEPrologue()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 156 Register SPReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
157 MIRBuilder.buildCopy(SPReg, Register(AArch64::SP)); in getStackAddress()
163 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
|