/external/llvm-project/llvm/lib/Target/Mips/ |
D | MipsExpandPseudo.cpp | 181 const unsigned ShiftImm = in expandAtomicCmpSwapSubword() local 185 .addImm(ShiftImm); in expandAtomicCmpSwapSubword() 188 .addImm(ShiftImm); in expandAtomicCmpSwapSubword() 557 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; in expandAtomicBinOpSubword() local 560 .addImm(ShiftImm); in expandAtomicBinOpSubword() 563 .addImm(ShiftImm); in expandAtomicBinOpSubword()
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D | MipsISelLowering.cpp | 1636 int64_t ShiftImm = 32 - (Size * 8); in emitSignExtendToI32InReg() local 1638 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); in emitSignExtendToI32InReg() 1639 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | MipsExpandPseudo.cpp | 181 const unsigned ShiftImm = in expandAtomicCmpSwapSubword() local 185 .addImm(ShiftImm); in expandAtomicCmpSwapSubword() 188 .addImm(ShiftImm); in expandAtomicCmpSwapSubword() 557 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; in expandAtomicBinOpSubword() local 560 .addImm(ShiftImm); in expandAtomicBinOpSubword() 563 .addImm(ShiftImm); in expandAtomicBinOpSubword()
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D | MipsISelLowering.cpp | 1638 int64_t ShiftImm = 32 - (Size * 8); in emitSignExtendToI32InReg() local 1640 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); in emitSignExtendToI32InReg() 1641 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64FastISel.cpp | 170 uint64_t ShiftImm, bool SetFlags = false, 175 uint64_t ShiftImm, bool SetFlags = false, 201 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, 209 uint64_t ShiftImm); 1277 unsigned ShiftImm; in emitAddSub_ri() local 1279 ShiftImm = 0; in emitAddSub_ri() 1281 ShiftImm = 12; in emitAddSub_ri() 1310 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitAddSub_ri() 1318 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rs() argument 1326 if (ShiftImm >= RetVT.getSizeInBits()) in emitAddSub_rs() [all …]
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D | AArch64ISelDAGToDAG.cpp | 1526 uint64_t ShiftImm; in isBitfieldExtractOpFromSExtInReg() local 1527 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) && in isBitfieldExtractOpFromSExtInReg() 1528 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in isBitfieldExtractOpFromSExtInReg() 1532 if (ShiftImm + Width > BitWidth) in isBitfieldExtractOpFromSExtInReg() 1537 Immr = ShiftImm; in isBitfieldExtractOpFromSExtInReg() 1538 Imms = ShiftImm + Width - 1; in isBitfieldExtractOpFromSExtInReg() 1662 uint64_t ShiftImm; in tryBitfieldExtractOpFromSExt() local 1664 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in tryBitfieldExtractOpFromSExt() 1670 unsigned Immr = ShiftImm; in tryBitfieldExtractOpFromSExt()
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/external/llvm-project/llvm/lib/Target/AArch64/ |
D | AArch64FastISel.cpp | 213 uint64_t ShiftImm, bool SetFlags = false, 218 uint64_t ShiftImm, bool SetFlags = false, 246 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, 254 uint64_t ShiftImm); 1358 unsigned ShiftImm; in emitAddSub_ri() local 1360 ShiftImm = 0; in emitAddSub_ri() 1362 ShiftImm = 12; in emitAddSub_ri() 1391 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitAddSub_ri() 1399 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rs() argument 1409 if (ShiftImm >= RetVT.getSizeInBits()) in emitAddSub_rs() [all …]
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D | AArch64ISelDAGToDAG.cpp | 1860 uint64_t ShiftImm; in isBitfieldExtractOpFromSExtInReg() local 1861 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) && in isBitfieldExtractOpFromSExtInReg() 1862 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in isBitfieldExtractOpFromSExtInReg() 1866 if (ShiftImm + Width > BitWidth) in isBitfieldExtractOpFromSExtInReg() 1871 Immr = ShiftImm; in isBitfieldExtractOpFromSExtInReg() 1872 Imms = ShiftImm + Width - 1; in isBitfieldExtractOpFromSExtInReg() 1997 uint64_t ShiftImm; in tryBitfieldExtractOpFromSExt() local 1999 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in tryBitfieldExtractOpFromSExt() 2005 unsigned Immr = ShiftImm; in tryBitfieldExtractOpFromSExt()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64FastISel.cpp | 213 uint64_t ShiftImm, bool SetFlags = false, 218 uint64_t ShiftImm, bool SetFlags = false, 246 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, 254 uint64_t ShiftImm); 1360 unsigned ShiftImm; in emitAddSub_ri() local 1362 ShiftImm = 0; in emitAddSub_ri() 1364 ShiftImm = 12; in emitAddSub_ri() 1393 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitAddSub_ri() 1401 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rs() argument 1411 if (ShiftImm >= RetVT.getSizeInBits()) in emitAddSub_rs() [all …]
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D | AArch64ISelDAGToDAG.cpp | 1679 uint64_t ShiftImm; in isBitfieldExtractOpFromSExtInReg() local 1680 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) && in isBitfieldExtractOpFromSExtInReg() 1681 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in isBitfieldExtractOpFromSExtInReg() 1685 if (ShiftImm + Width > BitWidth) in isBitfieldExtractOpFromSExtInReg() 1690 Immr = ShiftImm; in isBitfieldExtractOpFromSExtInReg() 1691 Imms = ShiftImm + Width - 1; in isBitfieldExtractOpFromSExtInReg() 1816 uint64_t ShiftImm; in tryBitfieldExtractOpFromSExt() local 1818 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in tryBitfieldExtractOpFromSExt() 1824 unsigned Immr = ShiftImm; in tryBitfieldExtractOpFromSExt()
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D | AArch64InstructionSelector.cpp | 1066 Optional<int64_t> ShiftImm = getVectorShiftImm(Reg, MRI); in getVectorSHLImm() local 1067 if (!ShiftImm) in getVectorSHLImm() 1070 int64_t Imm = *ShiftImm; in getVectorSHLImm()
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/external/llvm/lib/Target/ARM/AsmParser/ |
D | ARMAsmParser.cpp | 516 unsigned ShiftImm; // shift for OffsetReg. member 526 unsigned ShiftImm; member 538 unsigned ShiftImm; member 544 unsigned ShiftImm; member 1254 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || in isMemTBH() 1271 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) in isT2MemRegOffset() 1808 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands() 1817 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); in addRegShiftedImmOperands() 2131 Memory.ShiftImm, Memory.ShiftType); in addAddrMode2Operands() 2340 Memory.ShiftImm, Memory.ShiftType); in addMemRegOffsetOperands() [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
D | ARMAsmParser.cpp | 787 unsigned ShiftImm; // shift for OffsetReg. member 797 unsigned ShiftImm; member 809 unsigned ShiftImm; member 815 unsigned ShiftImm; member 1607 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || in isMemTBH() 1626 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) in isT2MemRegOffset() 1776 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift)) in isMemRegRQOffset() 2420 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands() 2429 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); in addRegShiftedImmOperands() 2820 Memory.ShiftImm, Memory.ShiftType); in addAddrMode2Operands() [all …]
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/external/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
D | ARMAsmParser.cpp | 853 unsigned ShiftImm; // shift for OffsetReg. member 863 unsigned ShiftImm; member 875 unsigned ShiftImm; member 881 unsigned ShiftImm; member 1673 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || in isMemTBH() 1692 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) in isT2MemRegOffset() 1842 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift)) in isMemRegRQOffset() 2486 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands() 2495 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); in addRegShiftedImmOperands() 2886 Memory.ShiftImm, Memory.ShiftType); in addAddrMode2Operands() [all …]
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/external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
D | ARMMCCodeEmitter.cpp | 949 unsigned Size, ShiftImm; in getMVEShiftImmOpValue() local 966 ShiftImm = MI.getOperand(OpIdx).getImm(); in getMVEShiftImmOpValue() 967 return Size + ShiftImm; in getMVEShiftImmOpValue()
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/external/llvm/lib/Target/ARM/ |
D | ARMFastISel.cpp | 2759 unsigned ShiftImm; in SelectShift() local 2762 ShiftImm = CI->getZExtValue(); in SelectShift() 2766 if (ShiftImm == 0 || ShiftImm >=32) in SelectShift() 2790 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMFastISel.cpp | 2780 unsigned ShiftImm; in SelectShift() local 2783 ShiftImm = CI->getZExtValue(); in SelectShift() 2787 if (ShiftImm == 0 || ShiftImm >=32) in SelectShift() 2811 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
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/external/llvm-project/llvm/lib/Target/ARM/ |
D | ARMFastISel.cpp | 2775 unsigned ShiftImm; in SelectShift() local 2778 ShiftImm = CI->getZExtValue(); in SelectShift() 2782 if (ShiftImm == 0 || ShiftImm >=32) in SelectShift() 2806 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
D | ARMMCCodeEmitter.cpp | 957 unsigned Size, ShiftImm; in getMVEShiftImmOpValue() local 974 ShiftImm = MI.getOperand(OpIdx).getImm(); in getMVEShiftImmOpValue() 975 return Size + ShiftImm; in getMVEShiftImmOpValue()
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/external/llvm-project/llvm/lib/Target/PowerPC/ |
D | PPCMIPeephole.cpp | 662 unsigned ShiftImm = DefMI->getOperand(3).getImm(); in simplifyCode() local 665 unsigned NewElem = (SplatImm + ShiftImm) & 0x3; in simplifyCode()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
D | PPCMIPeephole.cpp | 501 unsigned ShiftImm = DefMI->getOperand(3).getImm(); in simplifyCode() local 504 unsigned NewElem = (SplatImm + ShiftImm) & 0x3; in simplifyCode()
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/external/llvm/lib/Target/Mips/ |
D | MipsISelLowering.cpp | 1218 int64_t ShiftImm = 32 - (Size * 8); in emitSignExtendToI32InReg() local 1220 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); in emitSignExtendToI32InReg() 1221 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
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/external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
D | AArch64InstructionSelector.cpp | 1668 Optional<int64_t> ShiftImm = getVectorShiftImm(Reg, MRI); in getVectorSHLImm() local 1669 if (!ShiftImm) in getVectorSHLImm() 1672 int64_t Imm = *ShiftImm; in getVectorSHLImm()
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/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAG.cpp | 5305 APInt ShiftImm = N2C->getAPIntValue(); in getNode() local 5306 return getVScale(DL, VT, MulImm << ShiftImm); in getNode()
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