Searched refs:ShiftRHS (Results 1 – 6 of 6) sorted by relevance
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 4696 MachineOperand &ShiftRHS = ShiftInst->getOperand(2); in selectShiftedRegister() local
4697 auto Immed = getImmedFromMO(ShiftRHS); in selectShiftedRegister()
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| D | AArch64ISelLowering.cpp | 10126 uint32_t ShiftRHS = 0; in tryCombineToEXTR() local
10128 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi)) in tryCombineToEXTR()
10136 if (ShiftLHS + ShiftRHS != VT.getSizeInBits()) in tryCombineToEXTR()
10141 std::swap(ShiftLHS, ShiftRHS); in tryCombineToEXTR()
10145 DAG.getConstant(ShiftRHS, DL, MVT::i64)); in tryCombineToEXTR()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 7861 uint32_t ShiftRHS = 0; in tryCombineToEXTR() local
7863 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi)) in tryCombineToEXTR()
7871 if (ShiftLHS + ShiftRHS != VT.getSizeInBits()) in tryCombineToEXTR()
7876 std::swap(ShiftLHS, ShiftRHS); in tryCombineToEXTR()
7880 DAG.getConstant(ShiftRHS, DL, MVT::i64)); in tryCombineToEXTR()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 4964 const SDValue ShiftRHS = RHS.getOperand(1); in SelectSVERegRegAddrMode() local
4965 if (auto *C = dyn_cast<ConstantSDNode>(ShiftRHS)) in SelectSVERegRegAddrMode()
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| D | AArch64ISelLowering.cpp | 11988 uint32_t ShiftRHS = 0; in tryCombineToEXTR() local
11990 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi)) in tryCombineToEXTR()
11998 if (ShiftLHS + ShiftRHS != VT.getSizeInBits()) in tryCombineToEXTR()
12003 std::swap(ShiftLHS, ShiftRHS); in tryCombineToEXTR()
12007 DAG.getConstant(ShiftRHS, DL, MVT::i64)); in tryCombineToEXTR()
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| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64InstructionSelector.cpp | 5657 MachineOperand &ShiftRHS = ShiftInst->getOperand(2); in selectShiftedRegister() local
5658 auto Immed = getImmedFromMO(ShiftRHS); in selectShiftedRegister()
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