| /external/llvm-project/mlir/test/Conversion/SPIRVToLLVM/ |
| D | shift-ops-to-llvm.mlir | 44 // spv.ShiftRightLogical
50 %0 = spv.ShiftRightLogical %arg0, %arg0 : i32, i32
53 %1 = spv.ShiftRightLogical %arg0, %arg1 : i32, si32
57 %2 = spv.ShiftRightLogical %arg0, %arg2 : i32, si16
61 %3 = spv.ShiftRightLogical %arg0, %arg3 : i32, ui16
68 %0 = spv.ShiftRightLogical %arg0, %arg0 : vector<4xi64>, vector<4xi64>
71 %1 = spv.ShiftRightLogical %arg0, %arg1 : vector<4xi64>, vector<4xsi64>
75 %2 = spv.ShiftRightLogical %arg0, %arg2 : vector<4xi64>, vector<4xi32>
79 %3 = spv.ShiftRightLogical %arg0, %arg3 : vector<4xi64>, vector<4xui32>
|
| /external/deqp-deps/glslang/Test/baseResults/ |
| D | spv.shaderFragMaskAMD.frag.out | 81 32: 12(int) ShiftRightLogical 30 31
95 51: 12(int) ShiftRightLogical 50 31
110 69: 12(int) ShiftRightLogical 68 31
|
| D | spv.shiftOps.frag.out | 63 33: 17(ivec3) ShiftRightLogical 28 32
67 37: 17(ivec3) ShiftRightLogical 35 36
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| D | spv.rankShift.comp.out | 58 28: 6(int64_t) ShiftRightLogical 27 26
|
| D | hlsl.structbuffer.rwbyte.frag.out | 1097 25: 20(int) ShiftRightLogical 23 24
1101 29: 20(int) ShiftRightLogical 28 24
1107 36: 20(int) ShiftRightLogical 35 24
1111 40: 20(int) ShiftRightLogical 39 24
1127 57: 20(int) ShiftRightLogical 56 24
1141 71: 20(int) ShiftRightLogical 70 24
1145 75: 20(int) ShiftRightLogical 74 24
1165 94: 20(int) ShiftRightLogical 93 24
1185 112: 20(int) ShiftRightLogical 111 24
1203 130: 20(int) ShiftRightLogical 129 24
[all …]
|
| D | hlsl.structbuffer.byte.frag.out | 412 24: 20(int) ShiftRightLogical 22 23
418 34: 20(int) ShiftRightLogical 33 23
436 57: 20(int) ShiftRightLogical 56 23
458 82: 20(int) ShiftRightLogical 81 23
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| D | hlsl.shapeConv.frag.out | 451 90: 85(ivec3) ShiftRightLogical 86 89
455 94: 85(ivec3) ShiftRightLogical 91 93
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| D | hlsl.structbuffer.fn2.comp.out | 220 28: 23(int) ShiftRightLogical 26 27
|
| /external/llvm-project/mlir/test/Dialect/SPIRV/Serialization/ |
| D | bit-ops.mlir | 54 // CHECK: {{%.*}} = spv.ShiftRightLogical {{%.*}}, {{%.*}} : vector<2xi32>, vector<2xi8>
55 %0 = spv.ShiftRightLogical %arg0, %arg1: vector<2xi32>, vector<2xi8>
|
| /external/tensorflow/tensorflow/compiler/tf2xla/kernels/ |
| D | pooling_ops.cc | 590 auto bp_hi = xla::ShiftRightLogical(bp_int, sixteen); in Compile()
592 xla::ShiftRightLogical(xla::ShiftLeft(bp_int, sixteen), sixteen); in Compile()
607 xla::ShiftLeft(xla::ShiftRightLogical( in Compile()
611 xla::ShiftLeft(xla::ShiftRightLogical( in Compile()
630 auto grads_lo = xla::ShiftRightLogical( in Compile()
|
| D | cast_op.cc | 168 input = xla::And(xla::ShiftRightLogical(input, iota_m), in Compile()
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| D | binary_ops.cc | 197 ? xla::ShiftRightLogical(lhs, rhs, extend_dimensions)
|
| /external/tensorflow/tensorflow/compiler/xla/client/lib/ |
| D | prng.cc | 42 ShiftRightLogical(v, ConstantR0<uint32>(v.builder(), 32 - distance)); in RotateLeftU32()
126 XlaOp snd = ConvertElementType(ShiftRightLogical(u64, const32), U32); in Uint64ToUint32s()
483 bits = ShiftRightLogical( in ConvertRandomBitsToUniformFloatingPoint()
507 ShiftRightLogical(dist, ConstantR0WithType(builder, unsigned_type, 1)); in ConvertRandomBitsToUniformInt()
|
| D | quantize.h | 131 XlaOp shifted_input = ShiftRightLogical(
|
| /external/llvm-project/mlir/include/mlir/Dialect/SPIRV/ |
| D | SPIRVBitOps.td | 533 def SPV_ShiftRightLogicalOp : SPV_ShiftOp<"ShiftRightLogical", []> {
558 shift-right-logical-op ::= ssa-id `=` `spv.ShiftRightLogical`
567 %2 = spv.ShiftRightLogical %0, %1 : i32, i16
568 %5 = spv.ShiftRightLogical %3, %4 : vector<3xi32>, vector<3xi16>
|
| /external/swiftshader/third_party/SPIRV-Tools/source/ |
| D | assembly_grammar.cpp | 117 CASE(ShiftRightLogical),
|
| /external/deqp-deps/SPIRV-Tools/source/ |
| D | assembly_grammar.cpp | 117 CASE(ShiftRightLogical),
|
| /external/llvm-project/lldb/include/lldb/Utility/ |
| D | Scalar.h | 132 bool ShiftRightLogical(const Scalar &rhs); // Returns true on success
|
| /external/tensorflow/tensorflow/compiler/xla/service/ |
| D | hlo_matchers.h | 269 HLO_MATCHER(ShiftRightLogical);
|
| /external/swiftshader/third_party/SPIRV-Tools/test/ |
| D | text_to_binary.constant_test.cpp | 704 CASE2(ShiftRightLogical),
|
| /external/deqp-deps/SPIRV-Tools/test/ |
| D | text_to_binary.constant_test.cpp | 704 CASE2(ShiftRightLogical),
|
| /external/llvm-project/mlir/test/Dialect/SPIRV/ |
| D | ops.mlir | 1030 // spv.ShiftRightLogical
1034 // CHECK: {{%.*}} = spv.ShiftRightLogical {{%.*}}, {{%.*}} : vector<2xi32>, vector<2xi8>
1035 %0 = spv.ShiftRightLogical %arg0, %arg1: vector<2xi32>, vector<2xi8>
|
| /external/tensorflow/tensorflow/compiler/xla/python/ |
| D | ops.cc | 333 BINARY_OP(ShiftRightLogical); in BuildOpsSubmodule()
|
| /external/llvm-project/lldb/source/Utility/ |
| D | Scalar.cpp | 433 bool Scalar::ShiftRightLogical(const Scalar &rhs) { in ShiftRightLogical() function in Scalar
|
| /external/llvm-project/mlir/test/Conversion/StandardToSPIRV/ |
| D | std-ops-to-spirv.mlir | 243 // CHECK: spv.ShiftRightLogical
254 // CHECK: spv.ShiftRightLogical
|