/external/llvm/lib/Target/ARM/AsmParser/ |
D | ARMAsmParser.cpp | 525 ARM_AM::ShiftOpc ShiftTy; member 535 ARM_AM::ShiftOpc ShiftTy; member 542 ARM_AM::ShiftOpc ShiftTy; member 1088 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; in isPostIdxReg() 1209 return PostIdxReg.ShiftTy == ARM_AM::no_shift; in isAM3Offset() 1808 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands() 1819 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); in addRegShiftedImmOperands() 2423 PostIdxReg.ShiftTy); in addPostIdxRegShiftedOperands() 2653 Op->RegShiftedReg.ShiftTy = ShTy; in CreateShiftedRegister() 2666 Op->RegShiftedImm.ShiftTy = ShTy; in CreateShiftedImmediate() [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
D | ARMAsmParser.cpp | 796 ARM_AM::ShiftOpc ShiftTy; member 806 ARM_AM::ShiftOpc ShiftTy; member 813 ARM_AM::ShiftOpc ShiftTy; member 1380 return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift; in isPostIdxReg() 2420 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands() 2431 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); in addRegShiftedImmOperands() 3126 PostIdxReg.ShiftTy); in addPostIdxRegShiftedOperands() 3464 Op->RegShiftedReg.ShiftTy = ShTy; in CreateShiftedRegister() 3477 Op->RegShiftedImm.ShiftTy = ShTy; in CreateShiftedImmediate() 3644 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg() argument [all …]
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/external/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
D | ARMAsmParser.cpp | 862 ARM_AM::ShiftOpc ShiftTy; member 872 ARM_AM::ShiftOpc ShiftTy; member 879 ARM_AM::ShiftOpc ShiftTy; member 1446 return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift; in isPostIdxReg() 2486 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands() 2497 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); in addRegShiftedImmOperands() 3192 PostIdxReg.ShiftTy); in addPostIdxRegShiftedOperands() 3530 Op->RegShiftedReg.ShiftTy = ShTy; in CreateShiftedRegister() 3543 Op->RegShiftedImm.ShiftTy = ShTy; in CreateShiftedImmediate() 3709 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg() argument [all …]
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/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeIntegerTypes.cpp | 839 EVT ShiftTy = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout()); in PromoteIntRes_MULFIX() local 841 DAG.getConstant(DiffSize, dl, ShiftTy)); in PromoteIntRes_MULFIX() 846 DAG.getConstant(DiffSize, dl, ShiftTy)); in PromoteIntRes_MULFIX() 943 EVT ShiftTy = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout()); in PromoteIntRes_DIVFIX() local 948 DAG.getConstant(Diff, dl, ShiftTy)); in PromoteIntRes_DIVFIX() 953 DAG.getConstant(Diff, dl, ShiftTy)); in PromoteIntRes_DIVFIX() 1349 EVT ShiftTy = getShiftAmountTyForConstant(Mul.getValueType(), TLI, DAG); in PromoteIntRes_XMULO() local 1351 DAG.getConstant(Shift, DL, ShiftTy)); in PromoteIntRes_XMULO() 3418 EVT ShiftTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout()); in ExpandIntRes_MULFIX() local 3441 SDValue ShiftAmount = DAG.getConstant(Scale % NVTSize, dl, ShiftTy); in ExpandIntRes_MULFIX() [all …]
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D | TargetLowering.cpp | 3999 EVT ShiftTy = in SimplifySetCC() local 4008 DAG.getConstant(ShCt, dl, ShiftTy))); in SimplifySetCC() 4018 DAG.getConstant(ShCt, dl, ShiftTy))); in SimplifySetCC() 4026 EVT ShiftTy = getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); in SimplifySetCC() local 4037 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC() 4065 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC() 7740 EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout()); in expandFixedPointMul() local 7742 DAG.getConstant(Scale, dl, ShiftTy)); in expandFixedPointMul() 7770 DAG.getConstant(VTSize - 1, dl, ShiftTy)); in expandFixedPointMul() 7837 EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout()); in expandFixedPointDiv() local [all …]
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D | SelectionDAGBuilder.cpp | 3000 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( in visitShift() local 3004 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { in visitShift() 3005 unsigned ShiftSize = ShiftTy.getSizeInBits(); in visitShift() 3011 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); in visitShift() 3018 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); in visitShift() 5300 EVT ShiftTy = TLI.getShiftAmountTy(PromVT, DAG.getDataLayout()); in expandDivFix() local 5305 DAG.getConstant(1, DL, ShiftTy)); in expandDivFix() 5309 DAG.getConstant(1, DL, ShiftTy)); in expandDivFix()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeIntegerTypes.cpp | 771 EVT ShiftTy = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout()); in PromoteIntRes_MULFIX() local 773 DAG.getConstant(DiffSize, dl, ShiftTy)); in PromoteIntRes_MULFIX() 778 DAG.getConstant(DiffSize, dl, ShiftTy)); in PromoteIntRes_MULFIX() 1156 EVT ShiftTy = getShiftAmountTyForConstant(Mul.getValueType(), TLI, DAG); in PromoteIntRes_XMULO() local 1158 DAG.getConstant(Shift, DL, ShiftTy)); in PromoteIntRes_XMULO() 3086 EVT ShiftTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout()); in ExpandIntRes_MULFIX() local 3109 SDValue ShiftAmount = DAG.getConstant(Scale % NVTSize, dl, ShiftTy); in ExpandIntRes_MULFIX() 3151 DAG.getConstant(Scale, dl, ShiftTy)); in ExpandIntRes_MULFIX() 3161 ShiftTy)); in ExpandIntRes_MULFIX() 3355 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); in ExpandIntRes_Shift() local [all …]
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D | TargetLowering.cpp | 3689 EVT ShiftTy = in SimplifySetCC() local 3698 DAG.getConstant(ShCt, dl, ShiftTy))); in SimplifySetCC() 3708 DAG.getConstant(ShCt, dl, ShiftTy))); in SimplifySetCC() 3716 EVT ShiftTy = getShiftAmountTy(ShValTy, Layout, !DCI.isBeforeLegalize()); in SimplifySetCC() local 3727 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC() 3755 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC() 7255 EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout()); in expandFixedPointMul() local 7257 DAG.getConstant(Scale, dl, ShiftTy)); in expandFixedPointMul() 7285 DAG.getConstant(VTSize - 1, dl, ShiftTy)); in expandFixedPointMul() 7343 EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout()); in expandFixedPointDiv() local [all …]
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D | SelectionDAGBuilder.cpp | 3174 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( in visitShift() local 3178 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { in visitShift() 3179 unsigned ShiftSize = ShiftTy.getSizeInBits(); in visitShift() 3185 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); in visitShift() 3192 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); in visitShift()
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | TargetLowering.cpp | 1831 EVT ShiftTy = DCI.isBeforeLegalize() in SimplifySetCC() local 1840 ShiftTy))); in SimplifySetCC() 1849 ShiftTy))); in SimplifySetCC() 1865 EVT ShiftTy = DCI.isBeforeLegalize() in SimplifySetCC() local 1871 ShiftTy)); in SimplifySetCC() 1897 EVT ShiftTy = DCI.isBeforeLegalize() in SimplifySetCC() local 1902 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC()
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D | LegalizeIntegerTypes.cpp | 2363 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); in ExpandIntRes_Shift() local 2364 assert(ShiftTy.getScalarType().getSizeInBits() >= in ExpandIntRes_Shift() 2367 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift() 2368 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
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D | SelectionDAGBuilder.cpp | 2637 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( in visitShift() local 2641 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { in visitShift() 2642 unsigned ShiftSize = ShiftTy.getSizeInBits(); in visitShift() 2648 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); in visitShift() 2655 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); in visitShift()
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/external/llvm/lib/Target/Mips/ |
D | MipsSEISelLowering.cpp | 797 EVT ShiftTy, SelectionDAG &DAG) { in genConstMult() argument 812 DAG.getConstant(Log2_64(C), DL, ShiftTy)); in genConstMult() 822 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); in genConstMult() 823 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); in genConstMult() 829 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); in genConstMult() 830 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); in genConstMult()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | MipsSEISelLowering.cpp | 794 EVT ShiftTy, SelectionDAG &DAG) { in genConstMult() argument 806 DAG.getConstant(C.logBase2(), DL, ShiftTy)); in genConstMult() 817 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); in genConstMult() 818 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); in genConstMult() 824 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); in genConstMult() 825 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); in genConstMult()
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/external/llvm-project/llvm/lib/Target/Mips/ |
D | MipsSEISelLowering.cpp | 794 EVT ShiftTy, SelectionDAG &DAG) { in genConstMult() argument 806 DAG.getConstant(C.logBase2(), DL, ShiftTy)); in genConstMult() 817 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); in genConstMult() 818 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); in genConstMult() 824 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); in genConstMult() 825 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); in genConstMult()
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/external/llvm/lib/Target/ARM/ |
D | ARMFastISel.cpp | 156 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy); 2747 ARM_AM::ShiftOpc ShiftTy) { in SelectShift() argument 2790 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift() 2793 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0)); in SelectShift()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMFastISel.cpp | 186 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy); 2768 ARM_AM::ShiftOpc ShiftTy) { in SelectShift() argument 2811 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift() 2814 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0)); in SelectShift()
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/external/llvm-project/llvm/lib/Target/ARM/ |
D | ARMFastISel.cpp | 185 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy); 2763 ARM_AM::ShiftOpc ShiftTy) { in SelectShift() argument 2806 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift() 2809 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0)); in SelectShift()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
D | LegalizerHelper.cpp | 1376 LLT ShiftTy = SrcTy; in widenScalarExtract() local 1379 ShiftTy = WideTy; in widenScalarExtract() 1384 ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset)); in widenScalarExtract()
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/external/llvm-project/llvm/lib/Target/X86/ |
D | X86TargetTransformInfo.cpp | 3559 auto *ShiftTy = FixedVectorType::get( in getArithmeticReductionCost() local 3562 Instruction::LShr, ShiftTy, CostKind, in getArithmeticReductionCost() 3860 auto *ShiftTy = FixedVectorType::get( in getMinMaxReductionCost() local 3863 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, in getMinMaxReductionCost()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64InstructionSelector.cpp | 1267 const LLT ShiftTy = MRI.getType(ShiftReg); in preISelLower() local 1271 assert(!ShiftTy.isVector() && "unexpected vector shift ty"); in preISelLower() 1272 if (SrcTy.getSizeInBits() != 32 || ShiftTy.getSizeInBits() != 64) in preISelLower()
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/external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
D | CombinerHelper.cpp | 1751 LLT ShiftTy = MRI.getType(MI.getOperand(0).getReg()); in applyCombineMulToShl() local 1752 auto ShiftCst = MIB.buildConstant(ShiftTy, ShiftVal); in applyCombineMulToShl()
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D | LegalizerHelper.cpp | 1707 LLT ShiftTy = SrcTy; in widenScalarExtract() local 1710 ShiftTy = WideTy; in widenScalarExtract() 1714 ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset)); in widenScalarExtract()
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/external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
D | AArch64InstructionSelector.cpp | 1893 const LLT ShiftTy = MRI.getType(ShiftReg); in preISelLower() local 1897 assert(!ShiftTy.isVector() && "unexpected vector shift ty"); in preISelLower() 1898 if (SrcTy.getSizeInBits() != 32 || ShiftTy.getSizeInBits() != 64) in preISelLower()
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/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 28563 EVT ShiftTy = Shift.getValueType(); in foldXorTruncShiftIntoCmp() local 28564 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64) in foldXorTruncShiftIntoCmp() 28569 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1) in foldXorTruncShiftIntoCmp()
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