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Searched refs:SrcBit (Results 1 – 3 of 3) sorted by relevance

/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringX86BaseImpl.h6156 constexpr SizeT SrcBit = 1 << 2;
6157 assert((Index0 & SrcBit) == (Index1 & SrcBit));
6158 assert((Index0 & SrcBit) == (Index2 & SrcBit));
6159 assert((Index0 & SrcBit) == (Index3 & SrcBit));
6160 (void)SrcBit;
6175 constexpr SizeT SrcBit = 1 << 2;
6176 assert((Index0 & SrcBit) == (Index1 & SrcBit) || (Index1 == IGNORE_INDEX));
6177 assert((Index2 & SrcBit) == (Index3 & SrcBit) || (Index3 == IGNORE_INDEX));
6178 (void)SrcBit;
6201 constexpr SizeT SrcBit = 1 << 2;
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/external/llvm/utils/TableGen/
DCodeGenRegisters.cpp1215 unsigned SrcBit = NextBit; in computeSubRegLaneMasks() local
1216 unsigned SrcMask = 1u << SrcBit; in computeSubRegLaneMasks()
1231 int Shift = DstBit - SrcBit; in computeSubRegLaneMasks()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenRegisters.cpp1493 unsigned SrcBit = NextBit; in computeSubRegLaneMasks() local
1494 LaneBitmask SrcMask = LaneBitmask::getLane(SrcBit); in computeSubRegLaneMasks()
1509 int Shift = DstBit - SrcBit; in computeSubRegLaneMasks()