Home
last modified time | relevance | path

Searched refs:SrcVec (Results 1 – 25 of 29) sorted by relevance

12

/external/swiftshader/third_party/subzero/src/
DIcePhiLoweringImpl.h65 auto *SrcVec = llvm::cast<VariableVecOn32>(Src); in prelowerPhis32Bit() local
66 PhiElem->addArgument(SrcVec->getContainers()[Idx], Label); in prelowerPhis32Bit()
DIceTargetLoweringMIPS32.cpp5476 auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(legalizeUndef(Src0)); in lowerRet() local
5478 legalizeToReg(SrcVec->getContainers()[0], RegMIPS32::Reg_V0); in lowerRet()
5480 legalizeToReg(SrcVec->getContainers()[1], RegMIPS32::Reg_V1); in lowerRet()
5482 legalizeToReg(SrcVec->getContainers()[2], RegMIPS32::Reg_A0); in lowerRet()
5484 legalizeToReg(SrcVec->getContainers()[3], RegMIPS32::Reg_A1); in lowerRet()
5492 auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(legalizeUndef(Src0)); in lowerRet() local
5496 for (SizeT i = 0; i < SrcVec->ContainersPerVector; ++i) { in lowerRet()
5500 Variable *Var = legalizeToReg(SrcVec->getContainers()[i]); in lowerRet()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp205 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() local
217 .addReg(SrcVec) in RebuildVector()
228 SrcVec = DstReg; in RebuildVector()
231 BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec); in RebuildVector()
DSIISelLowering.cpp3495 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in emitIndirectDst() local
3499 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg()); in emitIndirectDst()
3506 SrcVec->getReg(), in emitIndirectDst()
3517 .add(*SrcVec) in emitIndirectDst()
3531 .addReg(SrcVec->getReg(), RegState::Undef, SubReg) // vdst in emitIndirectDst()
3534 .addReg(SrcVec->getReg(), RegState::Implicit) in emitIndirectDst()
3543 .addReg(SrcVec->getReg()) in emitIndirectDst()
3559 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, in emitIndirectDst()
6094 SDValue SrcVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, in LowerINTRINSIC_WO_CHAIN() local
6097 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec, in LowerINTRINSIC_WO_CHAIN()
/external/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp187 unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() local
199 .addReg(SrcVec) in RebuildVector()
212 SrcVec = DstReg; in RebuildVector()
215 BuildMI(MBB, Pos, DL, TII->get(AMDGPU::COPY), Reg).addReg(SrcVec); in RebuildVector()
DSILowerControlFlow.cpp633 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in indirectSrc() local
637 std::tie(Reg, Offset) = computeIndirectRegAndOffset(SrcVec->getReg(), Offset); in indirectSrc()
643 .addReg(Reg, getUndefRegState(SrcVec->isUndef())); in indirectSrc()
650 .addReg(Reg, getUndefRegState(SrcVec->isUndef())) in indirectSrc()
651 .addReg(SrcVec->getReg(), RegState::Implicit); in indirectSrc()
/external/llvm-project/llvm/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp337 Value *SrcVec = EI.getVectorOperand(); in visitExtractElementInst() local
339 if (Value *V = SimplifyExtractElementInst(SrcVec, Index, in visitExtractElementInst()
361 if (SrcVec->hasOneUse()) { in visitExtractElementInst()
366 SimplifyDemandedVectorElts(SrcVec, DemandedElts, UndefElts)) in visitExtractElementInst()
371 APInt DemandedElts = findDemandedEltsByAllUsers(SrcVec); in visitExtractElementInst()
375 SrcVec, DemandedElts, UndefElts, 0 /* Depth */, in visitExtractElementInst()
377 if (V != SrcVec) { in visitExtractElementInst()
378 SrcVec->replaceAllUsesWith(V); in visitExtractElementInst()
390 if (auto *Phi = dyn_cast<PHINode>(SrcVec)) in visitExtractElementInst()
398 if (match(SrcVec, m_UnOp(UO)) && cheapToScalarize(SrcVec, IndexC)) { in visitExtractElementInst()
[all …]
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp209 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() local
221 .addReg(SrcVec) in RebuildVector()
232 SrcVec = DstReg; in RebuildVector()
235 BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec); in RebuildVector()
DAMDGPUInstructionSelector.cpp2810 Register SrcVec = normalizeVOP3PMask(Mask, Src0Reg, Src1Reg, ShufMask); in selectG_SHUFFLE_VECTOR() local
2813 !RBI.constrainGenericRegister(SrcVec, RC, *MRI)) in selectG_SHUFFLE_VECTOR()
2819 .addReg(SrcVec); in selectG_SHUFFLE_VECTOR()
2829 .addReg(SrcVec); in selectG_SHUFFLE_VECTOR()
2832 .addReg(SrcVec) in selectG_SHUFFLE_VECTOR()
2839 .addReg(SrcVec); in selectG_SHUFFLE_VECTOR()
2842 .addReg(SrcVec) in selectG_SHUFFLE_VECTOR()
2851 .addReg(SrcVec) // $src0 in selectG_SHUFFLE_VECTOR()
2856 .addReg(SrcVec, RegState::Implicit); in selectG_SHUFFLE_VECTOR()
2860 .addReg(SrcVec) in selectG_SHUFFLE_VECTOR()
[all …]
DSIISelLowering.cpp3754 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in emitIndirectDst() local
3758 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg()); in emitIndirectDst()
3766 SrcVec->getReg(), in emitIndirectDst()
3777 .add(*SrcVec) in emitIndirectDst()
3796 .addReg(SrcVec->getReg()) in emitIndirectDst()
3806 .addReg(SrcVec->getReg()) in emitIndirectDst()
3823 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, Offset, in emitIndirectDst()
6718 SDValue SrcVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, in LowerINTRINSIC_WO_CHAIN() local
6721 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec, in LowerINTRINSIC_WO_CHAIN()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp320 Value *SrcVec = EI.getVectorOperand(); in visitExtractElementInst() local
322 if (Value *V = SimplifyExtractElementInst(SrcVec, Index, in visitExtractElementInst()
340 if (SrcVec->hasOneUse()) { in visitExtractElementInst()
345 SimplifyDemandedVectorElts(SrcVec, DemandedElts, UndefElts)) { in visitExtractElementInst()
352 APInt DemandedElts = findDemandedEltsByAllUsers(SrcVec); in visitExtractElementInst()
356 SrcVec, DemandedElts, UndefElts, 0 /* Depth */, in visitExtractElementInst()
358 if (V != SrcVec) { in visitExtractElementInst()
359 SrcVec->replaceAllUsesWith(V); in visitExtractElementInst()
371 if (auto *Phi = dyn_cast<PHINode>(SrcVec)) in visitExtractElementInst()
377 if (match(SrcVec, m_BinOp(BO)) && cheapToScalarize(SrcVec, IndexC)) { in visitExtractElementInst()
[all …]
/external/llvm/lib/IR/
DVerifier.cpp2318 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
2321 Assert(SrcVec == DstVec, in visitUIToFPInst()
2328 if (SrcVec && DstVec) in visitUIToFPInst()
2341 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
2344 Assert(SrcVec == DstVec, in visitSIToFPInst()
2351 if (SrcVec && DstVec) in visitSIToFPInst()
2364 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
2367 Assert(SrcVec == DstVec, in visitFPToUIInst()
2374 if (SrcVec && DstVec) in visitFPToUIInst()
2387 bool SrcVec = SrcTy->isVectorTy(); in visitFPToSIInst() local
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/IR/
DVerifier.cpp2662 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
2665 Assert(SrcVec == DstVec, in visitUIToFPInst()
2672 if (SrcVec && DstVec) in visitUIToFPInst()
2685 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
2688 Assert(SrcVec == DstVec, in visitSIToFPInst()
2695 if (SrcVec && DstVec) in visitSIToFPInst()
2708 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
2711 Assert(SrcVec == DstVec, in visitFPToUIInst()
2718 if (SrcVec && DstVec) in visitFPToUIInst()
2731 bool SrcVec = SrcTy->isVectorTy(); in visitFPToSIInst() local
[all …]
/external/llvm-project/llvm/lib/ExecutionEngine/Interpreter/
DExecution.cpp1549 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
1561 SrcVec = Src; in executeBitCastInst()
1567 SrcVec.AggregateVal.push_back(Src); in executeBitCastInst()
1588 APInt::floatToBits(SrcVec.AggregateVal[i].FloatVal); in executeBitCastInst()
1593 APInt::doubleToBits(SrcVec.AggregateVal[i].DoubleVal); in executeBitCastInst()
1596 TempSrc.AggregateVal[i].IntVal = SrcVec.AggregateVal[i].IntVal; in executeBitCastInst()
/external/llvm/lib/ExecutionEngine/Interpreter/
DExecution.cpp1501 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
1513 SrcVec = Src; in executeBitCastInst()
1519 SrcVec.AggregateVal.push_back(Src); in executeBitCastInst()
1540 APInt::floatToBits(SrcVec.AggregateVal[i].FloatVal); in executeBitCastInst()
1545 APInt::doubleToBits(SrcVec.AggregateVal[i].DoubleVal); in executeBitCastInst()
1548 TempSrc.AggregateVal[i].IntVal = SrcVec.AggregateVal[i].IntVal; in executeBitCastInst()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/ExecutionEngine/Interpreter/
DExecution.cpp1553 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
1565 SrcVec = Src; in executeBitCastInst()
1571 SrcVec.AggregateVal.push_back(Src); in executeBitCastInst()
1592 APInt::floatToBits(SrcVec.AggregateVal[i].FloatVal); in executeBitCastInst()
1597 APInt::doubleToBits(SrcVec.AggregateVal[i].DoubleVal); in executeBitCastInst()
1600 TempSrc.AggregateVal[i].IntVal = SrcVec.AggregateVal[i].IntVal; in executeBitCastInst()
/external/llvm-project/llvm/lib/IR/
DVerifier.cpp2804 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
2807 Assert(SrcVec == DstVec, in visitUIToFPInst()
2814 if (SrcVec && DstVec) in visitUIToFPInst()
2827 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
2830 Assert(SrcVec == DstVec, in visitSIToFPInst()
2837 if (SrcVec && DstVec) in visitSIToFPInst()
2850 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
2853 Assert(SrcVec == DstVec, in visitFPToUIInst()
2860 if (SrcVec && DstVec) in visitFPToUIInst()
2873 bool SrcVec = SrcTy->isVectorTy(); in visitFPToSIInst() local
[all …]
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp2449 Register SrcVec = MI.getOperand(1).getReg(); in bitcastExtractVectorElt() local
2451 LLT SrcVecTy = MRI.getType(SrcVec); in bitcastExtractVectorElt()
2459 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); in bitcastExtractVectorElt()
2588 Register SrcVec = MI.getOperand(1).getReg(); in bitcastInsertVectorElt() local
2603 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); in bitcastInsertVectorElt()
3653 Register SrcVec = MI.getOperand(1).getReg(); in fewerElementsVectorExtractInsertVectorElt() local
3667 LLT VecTy = MRI.getType(SrcVec); in fewerElementsVectorExtractInsertVectorElt()
3681 LLT GCDTy = extractGCDType(VecParts, VecTy, NarrowVecTy, SrcVec); in fewerElementsVectorExtractInsertVectorElt()
5638 Register SrcVec = MI.getOperand(1).getReg(); in lowerExtractInsertVectorElt() local
5645 LLT VecTy = MRI.getType(SrcVec); in lowerExtractInsertVectorElt()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp7325 SDValue SrcVec = SrcExtract.getOperand(0); in getFauxShuffleMask() local
7326 EVT SrcVT = SrcVec.getValueType(); in getFauxShuffleMask()
7334 Ops.push_back(SrcVec); in getFauxShuffleMask()
9549 static SDValue createVariablePermute(MVT VT, SDValue SrcVec, SDValue IndicesVec, in createVariablePermute() argument
9566 if (SrcVec.getValueSizeInBits() != SizeInBits) { in createVariablePermute()
9567 if ((SrcVec.getValueSizeInBits() % SizeInBits) == 0) { in createVariablePermute()
9569 unsigned Scale = SrcVec.getValueSizeInBits() / SizeInBits; in createVariablePermute()
9575 createVariablePermute(VT, SrcVec, IndicesVec, DL, DAG, Subtarget), 0, in createVariablePermute()
9577 } else if (SrcVec.getValueSizeInBits() < SizeInBits) { in createVariablePermute()
9579 SrcVec = widenSubVector(VT, SrcVec, false, Subtarget, DAG, SDLoc(SrcVec)); in createVariablePermute()
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86ISelLowering.cpp7617 SDValue SrcVec = SrcExtract.getOperand(0); in getFauxShuffleMask() local
7618 EVT SrcVT = SrcVec.getValueType(); in getFauxShuffleMask()
7629 Ops.push_back(SrcVec); in getFauxShuffleMask()
7632 Ops.push_back(SrcVec); in getFauxShuffleMask()
9833 static SDValue createVariablePermute(MVT VT, SDValue SrcVec, SDValue IndicesVec, in createVariablePermute() argument
9850 if (SrcVec.getValueSizeInBits() != SizeInBits) { in createVariablePermute()
9851 if ((SrcVec.getValueSizeInBits() % SizeInBits) == 0) { in createVariablePermute()
9853 unsigned Scale = SrcVec.getValueSizeInBits() / SizeInBits; in createVariablePermute()
9859 createVariablePermute(VT, SrcVec, IndicesVec, DL, DAG, Subtarget); in createVariablePermute()
9863 } else if (SrcVec.getValueSizeInBits() < SizeInBits) { in createVariablePermute()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp418 auto IsBuildFromExtracts = [this,&Values] (SDValue &SrcVec, in buildHvxVectorReg()
440 SrcVec = Vec; in buildHvxVectorReg()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp545 auto IsBuildFromExtracts = [this,&Values] (SDValue &SrcVec, in buildHvxVectorReg()
567 SrcVec = Vec; in buildHvxVectorReg()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp4239 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; in lowerShuffleVector() local
4242 auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK); in lowerShuffleVector()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp5686 SDValue SrcVec = V1; in LowerVECTOR_SHUFFLE() local
5689 SrcVec = V2; in LowerVECTOR_SHUFFLE()
5701 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV), in LowerVECTOR_SHUFFLE()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp7353 SDValue SrcVec = V1; in LowerVECTOR_SHUFFLE() local
7356 SrcVec = V2; in LowerVECTOR_SHUFFLE()
7368 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV), in LowerVECTOR_SHUFFLE()

12