| /external/vixl/examples/aarch64/ |
| D | add2-vectors.cc | 77 __ Strb(w5, MemOperand(x0, 1, PostIndex)); in GenerateAdd2Vectors() local
|
| /external/vixl/examples/aarch32/ |
| D | mandelbrot.cc | 180 __ Strb(kZero, MemOperand(kWriteCursor)); in GenerateMandelBrot() local
|
| /external/vixl/benchmarks/aarch64/ |
| D | bench-utils.cc | 259 __ Strb(PickW(), MemOperand(scratch, 42)); in GenerateMemOperandSequence() local
|
| /external/vixl/test/aarch32/ |
| D | test-disasm-a32.cc | 3605 COMPARE_T32(Strb(eq, r6, MemOperand(r7, 31)), in TEST()
3609 COMPARE_T32(Strb(eq, r6, MemOperand(r7, 32)), in TEST()
3614 COMPARE_T32(Strb(eq, r5, MemOperand(r6, r7)), in TEST()
3618 COMPARE_T32(Strb(eq, r6, MemOperand(r9)), in TEST()
|
| D | test-simulator-cond-rd-memop-immediate-8192-a32.cc | 119 M(Strb)
|
| D | test-simulator-cond-rd-memop-rs-a32.cc | 122 M(Strb) \
|
| D | test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc | 119 M(Strb)
|
| D | test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc | 119 M(Strb)
|
| /external/vixl/test/aarch64/ |
| D | test-simulator-aarch64.cc | 742 __ Strb(flags, MemOperand(out, 1, PostIndex)); in TestCmp_Helper() local
877 __ Strb(flags, MemOperand(out, 1, PostIndex)); in TestCmpZero_Helper() local
|
| D | test-assembler-aarch64.cc | 2880 __ Strb(w3, MemOperand(x18, 25)); in TEST() local
2978 __ Strb(w3, MemOperand(x24, 25, PreIndex)); in TEST() local
3036 __ Strb(w3, MemOperand(x24, 5, PostIndex)); in TEST() local
3738 __ Strb(w3, MemOperand(x21, -1)); in TEST() local
13640 __ Strb(w10, MemOperand(sp, -1)); in TEST() local
|
| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 4431 void Strb(Condition cond, Register rt, const MemOperand& operand) { in Strb() function
4451 void Strb(Register rt, const MemOperand& operand) { Strb(al, rt, operand); } in Strb() function
|
| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 50 V(Strb, Register&, rt, STRB_w) \
|