| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 605 unsigned SubReg2 = OperandMasks[J].SubReg; in collectCandidates() local
612 " and " << printReg(Reg2, SubReg2) << '\n'); in collectCandidates()
620 unsigned FreeBanks2 = getFreeBanks(Reg2, SubReg2, Mask2, UsedBanks); in collectCandidates()
626 Candidate(&MI, Reg2, SubReg2, FreeBanks2)); in collectCandidates()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 543 unsigned SubReg2 = OperandMasks[J].SubReg; in collectCandidates() local
550 " and " << printReg(Reg2, SubReg2) << '\n'); in collectCandidates()
558 unsigned FreeBanks2 = getFreeBanks(Reg2, SubReg2, Mask2, UsedBanks); in collectCandidates()
|
| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 148 unsigned SubReg2 = MI.getOperand(Idx2).getSubReg(); in commuteInstructionImpl() local
161 SubReg0 = SubReg2; in commuteInstructionImpl()
185 CommutedMI->getOperand(Idx1).setSubReg(SubReg2); in commuteInstructionImpl()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 189 unsigned SubReg2 = MI.getOperand(Idx2).getSubReg(); in commuteInstructionImpl() local
210 SubReg0 = SubReg2; in commuteInstructionImpl()
234 CommutedMI->getOperand(Idx1).setSubReg(SubReg2); in commuteInstructionImpl()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 179 unsigned SubReg2 = MI.getOperand(Idx2).getSubReg(); in commuteInstructionImpl() local
200 SubReg0 = SubReg2; in commuteInstructionImpl()
224 CommutedMI->getOperand(Idx1).setSubReg(SubReg2); in commuteInstructionImpl()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 352 unsigned SubReg2 = MI.getOperand(2).getSubReg(); in commuteInstructionImpl() local
390 MI.getOperand(0).setSubReg(SubReg2); in commuteInstructionImpl()
395 MI.getOperand(1).setSubReg(SubReg2); in commuteInstructionImpl()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1647 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, dl, MVT::i32); in createQuadSRegsNode() local
1650 V2, SubReg2, V3, SubReg3 }; in createQuadSRegsNode()
1662 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, dl, MVT::i32); in createQuadDRegsNode() local
1665 V2, SubReg2, V3, SubReg3 }; in createQuadDRegsNode()
1677 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, dl, MVT::i32); in createQuadQRegsNode() local
1680 V2, SubReg2, V3, SubReg3 }; in createQuadQRegsNode()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1827 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, dl, MVT::i32); in createQuadSRegsNode() local
1830 V2, SubReg2, V3, SubReg3 }; in createQuadSRegsNode()
1842 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, dl, MVT::i32); in createQuadDRegsNode() local
1845 V2, SubReg2, V3, SubReg3 }; in createQuadDRegsNode()
1857 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, dl, MVT::i32); in createQuadQRegsNode() local
1860 V2, SubReg2, V3, SubReg3 }; in createQuadQRegsNode()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1874 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, dl, MVT::i32); in createQuadSRegsNode() local
1877 V2, SubReg2, V3, SubReg3 }; in createQuadSRegsNode()
1889 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, dl, MVT::i32); in createQuadDRegsNode() local
1892 V2, SubReg2, V3, SubReg3 }; in createQuadDRegsNode()
1904 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, dl, MVT::i32); in createQuadQRegsNode() local
1907 V2, SubReg2, V3, SubReg3 }; in createQuadQRegsNode()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 399 unsigned SubReg2 = MI.getOperand(2).getSubReg(); in commuteInstructionImpl() local
437 MI.getOperand(0).setSubReg(SubReg2); in commuteInstructionImpl()
442 MI.getOperand(1).setSubReg(SubReg2); in commuteInstructionImpl()
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 740 unsigned SubReg2 = MI.getOperand(2).getSubReg(); in commuteInstructionImpl() local
778 MI.getOperand(0).setSubReg(SubReg2); in commuteInstructionImpl()
783 MI.getOperand(1).setSubReg(SubReg2); in commuteInstructionImpl()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 12897 unsigned SubReg1 = AArch64::sube64, SubReg2 = AArch64::subo64; in ReplaceCMP_SWAP_128Results() local
12899 std::swap(SubReg1, SubReg2); in ReplaceCMP_SWAP_128Results()
12902 Results.push_back(DAG.getTargetExtractSubreg(SubReg2, SDLoc(N), MVT::i64, in ReplaceCMP_SWAP_128Results()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 15800 unsigned SubReg1 = AArch64::sube64, SubReg2 = AArch64::subo64; in ReplaceCMP_SWAP_128Results() local
15802 std::swap(SubReg1, SubReg2); in ReplaceCMP_SWAP_128Results()
15805 SDValue Hi = DAG.getTargetExtractSubreg(SubReg2, SDLoc(N), MVT::i64, in ReplaceCMP_SWAP_128Results()
|