| /external/llvm/lib/Target/AVR/ |
| D | AVRTargetMachine.cpp | 49 SubTarget(TT, getCPU(CPU), FS, *this) { in AVRTargetMachine()
82 return &SubTarget; in getSubtargetImpl()
86 return &SubTarget; in getSubtargetImpl()
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| D | AVRTargetMachine.h | 46 AVRSubtarget SubTarget; variable
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRTargetMachine.cpp | 52 SubTarget(TT, getCPU(CPU), FS, *this) { in AVRTargetMachine()
89 return &SubTarget; in getSubtargetImpl()
93 return &SubTarget; in getSubtargetImpl()
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| D | AVRTargetMachine.h | 51 AVRSubtarget SubTarget; variable
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| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRTargetMachine.cpp | 52 SubTarget(TT, std::string(getCPU(CPU)), std::string(FS), *this) { in AVRTargetMachine()
89 return &SubTarget; in getSubtargetImpl()
93 return &SubTarget; in getSubtargetImpl()
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| D | AVRTargetMachine.h | 51 AVRSubtarget SubTarget; variable
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86IndirectBranchTracking.cpp | 100 const X86Subtarget &SubTarget = MF.getSubtarget<X86Subtarget>(); in runOnMachineFunction() local
111 TII = SubTarget.getInstrInfo(); in runOnMachineFunction()
112 EndbrOpcode = SubTarget.is64Bit() ? X86::ENDBR64 : X86::ENDBR32; in runOnMachineFunction()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86IndirectBranchTracking.cpp | 99 const X86Subtarget &SubTarget = MF.getSubtarget<X86Subtarget>(); in runOnMachineFunction() local
119 TII = SubTarget.getInstrInfo(); in runOnMachineFunction()
120 EndbrOpcode = SubTarget.is64Bit() ? X86::ENDBR64 : X86::ENDBR32; in runOnMachineFunction()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrFormats.td | 31 class SubTarget<bits<6> value> {
35 def HasAnySubT : SubTarget<0x3f>; // 111111
36 def HasV5SubT : SubTarget<0x3e>; // 111110
37 def HasV55SubT : SubTarget<0x3c>; // 111100
38 def HasV60SubT : SubTarget<0x38>; // 111000
157 SubTarget validSubTargets = HasAnySubT;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonBaseInfo.h | 30 enum SubTarget { enum
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonBaseInfo.h | 70 enum SubTarget { enum
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| D | HexagonMCInstrInfo.cpp | 356 HexagonII::SubTarget Target = static_cast<HexagonII::SubTarget>( in getSubTarget()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MIRPrinter.cpp | 708 const auto &SubTarget = MF->getSubtarget(); in print() local
709 const auto *TRI = SubTarget.getRegisterInfo(); in print()
711 const auto *TII = SubTarget.getInstrInfo(); in print()
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| /external/llvm/lib/CodeGen/ |
| D | MIRPrinter.cpp | 543 const auto &SubTarget = MF->getSubtarget(); in print() local
544 const auto *TRI = SubTarget.getRegisterInfo(); in print()
546 const auto *TII = SubTarget.getInstrInfo(); in print()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | MIRPrinter.cpp | 706 const auto &SubTarget = MF->getSubtarget(); in print() local
707 const auto *TRI = SubTarget.getRegisterInfo(); in print()
709 const auto *TII = SubTarget.getInstrInfo(); in print()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInsertWaitcnts.cpp | 198 WaitcntBrackets(const GCNSubtarget *SubTarget) : ST(SubTarget) { in WaitcntBrackets() argument
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInsertWaitcnts.cpp | 218 WaitcntBrackets(const GCNSubtarget *SubTarget) : ST(SubTarget) {} in WaitcntBrackets() argument
|