/external/llvm-project/llvm/lib/Transforms/InstCombine/ |
D | InstCombineCalls.cpp | 1657 Value *SubVec = II->getArgOperand(1); in visitCallInst() local 1661 auto *SubVecTy = dyn_cast<FixedVectorType>(SubVec->getType()); in visitCallInst() 1680 replaceInstUsesWith(CI, SubVec); in visitCallInst() 1696 SubVec, llvm::UndefValue::get(SubVecTy), WidenMask); in visitCallInst()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 5816 SDValue SubVec = Op.getOperand(1); in insert1BitVector() local 5823 if (SubVec.isUndef()) in insert1BitVector() 5846 SubVec, Idx); in insert1BitVector() 5850 MVT SubVecVT = SubVec.getSimpleValueType(); in insert1BitVector() 5867 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector() 5869 SubVec, ZeroIdx); in insert1BitVector() 5870 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec); in insert1BitVector() 5874 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector() 5875 Undef, SubVec, ZeroIdx); in insert1BitVector() 5879 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector() [all …]
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/external/llvm-project/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 6080 SDValue SubVec = Op.getOperand(1); in insert1BitVector() local 6085 if (SubVec.isUndef()) in insert1BitVector() 6106 SubVec, Idx); in insert1BitVector() 6110 MVT SubVecVT = SubVec.getSimpleValueType(); in insert1BitVector() 6126 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector() 6128 SubVec, ZeroIdx); in insert1BitVector() 6129 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec); in insert1BitVector() 6133 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector() 6134 Undef, SubVec, ZeroIdx); in insert1BitVector() 6138 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector() [all …]
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeVectorTypes.cpp | 848 SDValue SubVec = N->getOperand(1); in SplitVecRes_INSERT_SUBVECTOR() local 856 unsigned SubElems = SubVec.getValueType().getVectorNumElements(); in SplitVecRes_INSERT_SUBVECTOR() 869 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); in SplitVecRes_INSERT_SUBVECTOR() 883 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(), in SplitVecRes_INSERT_SUBVECTOR()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 8343 SDValue SubVec = DAG.getNode(ISD::UNDEF, dl, SubVT); in LowerEXTRACT_SUBVECTOR() local 8347 SubVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, SubVT, SubVec, Elt, in LowerEXTRACT_SUBVECTOR() 8353 return DAG.getNode(ARMISD::VCMPZ, dl, VT, SubVec, in LowerEXTRACT_SUBVECTOR() 13523 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, StoreType, in PerformTruncatingStoreCombine() local 13526 DAG.getStore(St->getChain(), DL, SubVec, BasePtr, St->getPointerInfo(), in PerformTruncatingStoreCombine() 17141 Value *SubVec = Builder.CreateExtractValue(VldN, Index); in lowerInterleavedLoad() local 17145 SubVec = Builder.CreateIntToPtr( in lowerInterleavedLoad() 17146 SubVec, VectorType::get(SV->getType()->getVectorElementType(), in lowerInterleavedLoad() 17149 SubVecs[SV].push_back(SubVec); in lowerInterleavedLoad() 17158 auto &SubVec = SubVecs[SVI]; in lowerInterleavedLoad() local [all …]
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/external/llvm-project/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 8649 SDValue SubVec = DAG.getNode(ISD::UNDEF, dl, SubVT); in LowerEXTRACT_SUBVECTOR() local 8653 SubVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, SubVT, SubVec, Elt, in LowerEXTRACT_SUBVECTOR() 8659 return DAG.getNode(ARMISD::VCMPZ, dl, VT, SubVec, in LowerEXTRACT_SUBVECTOR() 14632 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, StoreType, in PerformTruncatingStoreCombine() local 14635 DAG.getStore(St->getChain(), DL, SubVec, BasePtr, St->getPointerInfo(), in PerformTruncatingStoreCombine() 18967 Value *SubVec = Builder.CreateExtractValue(VldN, Index); in lowerInterleavedLoad() local 18971 SubVec = Builder.CreateIntToPtr( in lowerInterleavedLoad() 18972 SubVec, in lowerInterleavedLoad() 18975 SubVecs[SV].push_back(SubVec); in lowerInterleavedLoad() 18984 auto &SubVec = SubVecs[SVI]; in lowerInterleavedLoad() local [all …]
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/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeVectorTypes.cpp | 1225 SDValue SubVec = N->getOperand(1); in SplitVecRes_INSERT_SUBVECTOR() local 1232 unsigned SubElems = SubVec.getValueType().getVectorNumElements(); in SplitVecRes_INSERT_SUBVECTOR() 1244 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); in SplitVecRes_INSERT_SUBVECTOR() 1263 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, in SplitVecRes_INSERT_SUBVECTOR()
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D | SelectionDAGBuilder.cpp | 6939 SDValue SubVec = getValue(I.getOperand(1)); in visitIntrinsicCall() local 6942 setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ResultVT, Vec, SubVec, in visitIntrinsicCall()
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D | DAGCombiner.cpp | 17916 SDValue SubVec = InsertVal.getOperand(0); in combineInsertEltToShuffle() local 17918 EVT SubVecVT = SubVec.getValueType(); in combineInsertEltToShuffle() 17951 ConcatOps[0] = SubVec; in combineInsertEltToShuffle()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeVectorTypes.cpp | 1127 SDValue SubVec = N->getOperand(1); in SplitVecRes_INSERT_SUBVECTOR() local 1134 unsigned SubElems = SubVec.getValueType().getVectorNumElements(); in SplitVecRes_INSERT_SUBVECTOR() 1147 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); in SplitVecRes_INSERT_SUBVECTOR() 1161 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo()); in SplitVecRes_INSERT_SUBVECTOR()
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D | DAGCombiner.cpp | 16806 SDValue SubVec = InsertVal.getOperand(0); in combineInsertEltToShuffle() local 16808 EVT SubVecVT = SubVec.getValueType(); in combineInsertEltToShuffle() 16837 ConcatOps[0] = SubVec; in combineInsertEltToShuffle()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.cpp | 9207 Value *SubVec = Builder.CreateExtractValue(LdN, Index); in lowerInterleavedLoad() local 9211 SubVec = Builder.CreateIntToPtr( in lowerInterleavedLoad() 9212 SubVec, VectorType::get(SVI->getType()->getVectorElementType(), in lowerInterleavedLoad() 9214 SubVecs[SVI].push_back(SubVec); in lowerInterleavedLoad() 9223 auto &SubVec = SubVecs[SVI]; in lowerInterleavedLoad() local 9225 SubVec.size() > 1 ? concatenateVectors(Builder, SubVec) : SubVec[0]; in lowerInterleavedLoad()
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/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 4559 SDValue SubVec = Op.getOperand(1); in insert1BitVector() local 4570 MVT SubVecVT = SubVec.getSimpleValueType(); in insert1BitVector() 4594 Undef, SubVec, ZeroIdx); in insert1BitVector() 4630 SubVec, ZeroIdx); in insert1BitVector() 4649 SubVec, ZeroIdx); in insert1BitVector() 12753 SDValue SubVec = Op.getOperand(1); in LowerINSERT_SUBVECTOR() local 12761 MVT SubVecVT = SubVec.getSimpleValueType(); in LowerINSERT_SUBVECTOR() 12781 SDValue Ops[] = { SubVec2, SubVec }; in LowerINSERT_SUBVECTOR() 12791 return insert128BitVector(Vec, SubVec, IdxVal, DAG, dl); in LowerINSERT_SUBVECTOR() 12794 return insert256BitVector(Vec, SubVec, IdxVal, DAG, dl); in LowerINSERT_SUBVECTOR() [all …]
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/external/llvm-project/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.cpp | 10981 Value *SubVec = Builder.CreateExtractValue(LdN, Index); in lowerInterleavedLoad() local 10985 SubVec = Builder.CreateIntToPtr( in lowerInterleavedLoad() 10986 SubVec, FixedVectorType::get(SVI->getType()->getElementType(), in lowerInterleavedLoad() 10988 SubVecs[SVI].push_back(SubVec); in lowerInterleavedLoad() 10997 auto &SubVec = SubVecs[SVI]; in lowerInterleavedLoad() local 10999 SubVec.size() > 1 ? concatenateVectors(Builder, SubVec) : SubVec[0]; in lowerInterleavedLoad()
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/external/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 10310 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, in PerformSTORECombine() local 10313 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr, in PerformSTORECombine() 12625 Value *SubVec = Builder.CreateExtractValue(VldN, Index); in lowerInterleavedLoad() local 12629 SubVec = Builder.CreateIntToPtr(SubVec, SV->getType()); in lowerInterleavedLoad() 12631 SV->replaceAllUsesWith(SubVec); in lowerInterleavedLoad()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.cpp | 7139 Value *SubVec = Builder.CreateExtractValue(LdN, Index); in lowerInterleavedLoad() local 7143 SubVec = Builder.CreateIntToPtr(SubVec, SVI->getType()); in lowerInterleavedLoad() 7145 SVI->replaceAllUsesWith(SubVec); in lowerInterleavedLoad()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIISelLowering.cpp | 4952 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, in lowerVECTOR_SHUFFLE() local 4955 Pieces.push_back(SubVec); in lowerVECTOR_SHUFFLE()
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/external/llvm-project/llvm/lib/Target/AMDGPU/ |
D | SIISelLowering.cpp | 5539 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, in lowerVECTOR_SHUFFLE() local 5542 Pieces.push_back(SubVec); in lowerVECTOR_SHUFFLE()
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