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Searched refs:Successors (Results 1 – 25 of 106) sorted by relevance

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/external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/
Dside-effect-analysis-test.mlir14 // expected-remark@above {{Successors: {12}}}
18 // expected-remark@above {{Successors: {10}}}
21 // expected-remark@above {{Successors: {1}}}
25 // expected-remark@above {{Successors: {6}}}
28 // expected-remark@above {{Successors: {5}}}
33 // expected-remark@above {{Successors: {8}}}
37 // expected-remark@above {{Successors: {8}}}
41 // expected-remark@above {{Successors: {7}}}
45 // expected-remark@above {{Successors: {8}}}
69 // expected-remark@above {{Successors: {13}}}
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dcortex-a57-misched-vfma.ll13 ; CHECK: Successors:
22 ; CHECK: Successors:
30 ; CHECK: Successors:
52 ; CHECK: Successors:
61 ; CHECK: Successors:
69 ; CHECK: Successors:
90 ; CHECK: Successors:
99 ; CHECK: Successors:
107 ; CHECK: Successors:
129 ; CHECK: Successors:
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dmisched-fusion-arith-logic.mir15 ; CHECK: Successors:
18 ; CHECK: Successors:
37 ; CHECK: Successors:
40 ; CHECK: Successors:
59 ; CHECK: Successors:
62 ; CHECK: Successors:
79 ; CHECK: Successors:
89 ; CHECK: Successors:
101 ; CHECK: Successors:
104 ; CHECK: Successors:
Dmisched-fusion-crypto-eor.mir10 ; CHECK: Successors:
18 ; CHECK: Successors:
26 ; CHECK: Successors:
35 ; CHECK: Successors:
43 ; CHECK: Successors:
51 ; CHECK: Successors:
60 ; CHECK: Successors:
69 ; CHECK: Successors:
Dscheduledag-constreg.mir12 # CHECK-NOT: Successors:
15 # CHECK-NOT: Successors:
18 # CHECK-NOT: Successors:
21 # CHECK-NOT: Successors:
Darm64-misched-memdep-bug.ll9 ; CHECK: Successors:
13 ; CHECK: Successors:
/external/llvm/include/llvm/Analysis/
DInterval.h61 std::vector<BasicBlock*> Successors; variable
80 for (BasicBlock *Successor : Successors) in isSuccessor()
107 return I->Successors.begin(); in succ_begin()
110 return I->Successors.end(); in succ_end()
DIntervalIterator.h211 Int->Successors.push_back(NodeHeader); in ProcessNode()
218 Int->Successors.push_back(NodeHeader); in ProcessNode()
230 Int->Successors.erase(std::remove(Int->Successors.begin(), in ProcessNode()
231 Int->Successors.end(), NodeHeader), in ProcessNode()
232 Int->Successors.end()); in ProcessNode()
/external/llvm-project/llvm/include/llvm/Analysis/
DInterval.h59 std::vector<BasicBlock*> Successors; variable
77 for (BasicBlock *Successor : Successors) in isSuccessor()
103 return I->Successors.begin(); in succ_begin()
106 return I->Successors.end(); in succ_end()
DIntervalIterator.h211 Int->Successors.push_back(NodeHeader); in ProcessNode()
218 Int->Successors.push_back(NodeHeader); in ProcessNode()
230 Int->Successors.erase(std::remove(Int->Successors.begin(), in ProcessNode()
231 Int->Successors.end(), NodeHeader), in ProcessNode()
232 Int->Successors.end()); in ProcessNode()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Analysis/
DInterval.h59 std::vector<BasicBlock*> Successors; variable
77 for (BasicBlock *Successor : Successors) in isSuccessor()
103 return I->Successors.begin(); in succ_begin()
106 return I->Successors.end(); in succ_end()
DIntervalIterator.h211 Int->Successors.push_back(NodeHeader); in ProcessNode()
218 Int->Successors.push_back(NodeHeader); in ProcessNode()
230 Int->Successors.erase(std::remove(Int->Successors.begin(), in ProcessNode()
231 Int->Successors.end(), NodeHeader), in ProcessNode()
232 Int->Successors.end()); in ProcessNode()
/external/llvm/test/CodeGen/X86/
Dswitch-edge-weight.ll37 ; CHECK: Successors according to CFG: BB#4({{[0-9a-fx/= ]+}}72.22%) BB#5({{[0-9a-fx/= ]+}}27.78%)
42 ; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}76.92%) BB#7({{[0-9a-fx/= ]+}}23.08%)
47 ; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}40.00%) BB#6({{[0-9a-fx/= ]+}}60.00%)
52 ; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}66.67%) BB#2({{[0-9a-fx/= ]+}}33.33%)
105 ; CHECK: Successors according to CFG: BB#6({{[0-9a-fx/= ]+}}7.14%) BB#8({{[0-9a-fx/= ]+}}92.86%
114 ; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}15.38%) BB#6({{[0-9a-fx/= ]+}}7.69%) BB…
166 ; CHECK: Successors according to CFG: BB#6({{[0-9a-fx/= ]+}}16.67%) BB#8({{[0-9a-fx/= ]+}}83.33%)
174 ; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}20.00%) BB#2({{[0-9a-fx/= ]+}}20.00%) B…
219 ; CHECK: Successors according to CFG: BB#6({{[0-9a-fx/= ]+}}28.57%) BB#7({{[0-9a-fx/= ]+}}71.43%)
224 ; CHECK: Successors according to CFG: BB#2({{[0-9a-fx/= ]+}}60.00%) BB#3({{[0-9a-fx/= ]+}}40.00%)
[all …]
/external/llvm/test/CodeGen/Generic/
DMachineBranchProb.ll19 ; CHECK: Successors according to CFG: BB#2({{[0-9a-fx/= ]+}}75.29%) BB#4({{[0-9a-fx/= ]+}}24.71%)
21 ; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}47.62%) BB#5({{[0-9a-fx/= ]+}}52.38%)
23 ; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}36.36%) BB#3({{[0-9a-fx/= ]+}}63.64%)
64 ; CHECK-NOT: Successors
65 ; CHECK: Successors according to CFG: BB#8({{[0-9a-fx/= ]+}}39.71%) BB#9({{[0-9a-fx/= ]+}}60.29%)
/external/llvm/include/llvm/CodeGen/
DMachineBasicBlock.h94 std::vector<MachineBasicBlock *> Successors;
253 succ_iterator succ_begin() { return Successors.begin(); }
254 const_succ_iterator succ_begin() const { return Successors.begin(); }
255 succ_iterator succ_end() { return Successors.end(); }
256 const_succ_iterator succ_end() const { return Successors.end(); }
258 { return Successors.rbegin(); }
260 { return Successors.rbegin(); }
262 { return Successors.rend(); }
264 { return Successors.rend(); }
266 return (unsigned)Successors.size();
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Vectorize/
DVPlanVerifier.cpp58 const auto &Successors = VPB->getSuccessors(); in verifyBlocksInRegion() local
61 assert(!hasDuplicates(Successors) && in verifyBlocksInRegion()
64 for (const VPBlockBase *Succ : Successors) { in verifyBlocksInRegion()
/external/llvm-project/llvm/lib/Transforms/Vectorize/
DVPlanVerifier.cpp59 const auto &Successors = VPB->getSuccessors(); in verifyBlocksInRegion() local
62 assert(!hasDuplicates(Successors) && in verifyBlocksInRegion()
65 for (const VPBlockBase *Succ : Successors) { in verifyBlocksInRegion()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Support/
DDAGDeltaAlgorithm.cpp75 std::map<change_ty, std::vector<change_ty> > Successors; member in __anonf7cf2f1d0111::DAGDeltaAlgorithmImpl
100 assert(Successors.count(Node) && "Invalid node!"); in succ_begin()
101 return Successors[Node].begin(); in succ_begin()
104 assert(Successors.count(Node) && "Invalid node!"); in succ_end()
105 return Successors[Node].end(); in succ_end()
186 Successors.insert(std::make_pair(*it, std::vector<change_ty>())); in DAGDeltaAlgorithmImpl()
191 Successors[it->first].push_back(it->second); in DAGDeltaAlgorithmImpl()
/external/llvm-project/llvm/lib/Support/
DDAGDeltaAlgorithm.cpp75 std::map<change_ty, std::vector<change_ty> > Successors; member in __anon443717890111::DAGDeltaAlgorithmImpl
100 assert(Successors.count(Node) && "Invalid node!"); in succ_begin()
101 return Successors[Node].begin(); in succ_begin()
104 assert(Successors.count(Node) && "Invalid node!"); in succ_end()
105 return Successors[Node].end(); in succ_end()
186 Successors.insert(std::make_pair(*it, std::vector<change_ty>())); in DAGDeltaAlgorithmImpl()
191 Successors[it->first].push_back(it->second); in DAGDeltaAlgorithmImpl()
/external/llvm/lib/Support/
DDAGDeltaAlgorithm.cpp76 std::map<change_ty, std::vector<change_ty> > Successors; member in __anon7ef96bbb0111::DAGDeltaAlgorithmImpl
101 assert(Successors.count(Node) && "Invalid node!"); in succ_begin()
102 return Successors[Node].begin(); in succ_begin()
105 assert(Successors.count(Node) && "Invalid node!"); in succ_end()
106 return Successors[Node].end(); in succ_end()
187 Successors.insert(std::make_pair(*it, std::vector<change_ty>())); in DAGDeltaAlgorithmImpl()
192 Successors[it->first].push_back(it->second); in DAGDeltaAlgorithmImpl()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DMachineBasicBlock.h90 std::vector<MachineBasicBlock *> Successors;
280 succ_iterator succ_begin() { return Successors.begin(); }
281 const_succ_iterator succ_begin() const { return Successors.begin(); }
282 succ_iterator succ_end() { return Successors.end(); }
283 const_succ_iterator succ_end() const { return Successors.end(); }
285 { return Successors.rbegin(); }
287 { return Successors.rbegin(); }
289 { return Successors.rend(); }
291 { return Successors.rend(); }
293 return (unsigned)Successors.size();
[all …]
/external/llvm/test/CodeGen/ARM/Windows/
Ddbzchk.ll36 ; CHECK-DIV-DAG: Successors according to CFG: BB#5({{.*}}) BB#4
38 ; CHECK-DIV-DAG: Successors according to CFG: BB#3
40 ; CHECK-DIV-DAG: Successors according to CFG: BB#3
43 ; CHECK-DIV-DAG: Successors according to CFG: BB#1({{.*}}) BB#2
73 ; CHECK-MOD-DAG: Successors according to CFG: BB#2({{.*}}) BB#1
75 ; CHECK-MOD-DAG: Successors according to CFG: BB#4({{.*}}) BB#3
78 ; CHECK-MOD-DAG: Successors according to CFG: BB#2
/external/llvm-project/llvm/include/llvm/CodeGen/
DMachineBasicBlock.h120 std::vector<MachineBasicBlock *> Successors;
326 succ_iterator succ_begin() { return Successors.begin(); }
327 const_succ_iterator succ_begin() const { return Successors.begin(); }
328 succ_iterator succ_end() { return Successors.end(); }
329 const_succ_iterator succ_end() const { return Successors.end(); }
331 { return Successors.rbegin(); }
333 { return Successors.rbegin(); }
335 { return Successors.rend(); }
337 { return Successors.rend(); }
339 return (unsigned)Successors.size();
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-misched-memdep-bug.ll9 ; CHECK: Successors:
13 ; CHECK: Successors:
/external/llvm/test/CodeGen/ARM/
D2012-06-12-SchedMemLatency.ll16 ; CHECK: Successors:
26 ; CHECK: Successors:

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