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Searched refs:T54 (Results 1 – 5 of 5) sorted by relevance

/external/libcups/cups/
Dmd5.c100 # define T54 0x8f0ccc92 macro
249 SET(d, a, b, c, 3, 10, T54); in _cups_md5_process()
/external/python/cpython2/Modules/
Dmd5.c119 #define T54 /* 0x8f0ccc92 */ (T_MASK ^ 0x70f3336d) macro
291 SET(d, a, b, c, 3, 10, T54); in md5_process()
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
Dbad-reduction.ll391 ; CHECK-NEXT: [[T54:%.*]] = load i8, i8* [[T53]], align 1
407 ; CHECK-NEXT: [[T55:%.*]] = zext i8 [[T54]] to i32
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dload-global-i16.ll3921 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T54.XYZW, T56.X, 0
4011 ; EG-NEXT: LSHR T54.W, T52.W, literal.y,
4015 ; EG-NEXT: AND_INT T54.Z, T52.W, literal.x,
4019 ; EG-NEXT: LSHR T54.Y, T52.Z, literal.y,
4021 ; EG-NEXT: AND_INT * T54.X, T52.Z, literal.z,
4105 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T54, T51.X
4190 ; CM-NEXT: LSHR * T54.W, T51.Y, literal.y,
4193 ; CM-NEXT: AND_INT T54.Z, T51.Y, literal.x,
4197 ; CM-NEXT: LSHR T54.Y, T51.X, literal.y,
4200 ; CM-NEXT: AND_INT T54.X, T51.X, literal.x,
[all …]
Dload-constant-i16.ll3460 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T54.XYZW, T52.X, 0
3549 ; EG-NEXT: LSHR T54.W, T52.Y, literal.y,
3553 ; EG-NEXT: AND_INT T54.Z, T52.Y, literal.x,
3557 ; EG-NEXT: LSHR T54.Y, T52.X, literal.y,
3559 ; EG-NEXT: AND_INT * T54.X, T52.X, literal.z,
4188 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T64.XYZW, T54.X, 0
4252 ; EG-NEXT: LSHR T54.X, PS, literal.x,