Searched refs:T60 (Results 1 – 6 of 6) sorted by relevance
| /external/libcups/cups/ |
| D | md5.c | 106 # define T60 0x4e0811a1 macro
255 SET(b, c, d, a, 13, 21, T60); in _cups_md5_process()
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| /external/python/cpython2/Modules/ |
| D | md5.c | 125 #define T60 0x4e0811a1 macro
297 SET(b, c, d, a, 13, 21, T60); in md5_process()
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| /external/llvm-project/llvm/test/Transforms/SLPVectorizer/AArch64/ |
| D | getelementptr.ll | 255 ; CHECK-NEXT: [[T60:%.*]] = getelementptr inbounds i32, i32* [[P_0]], i64 [[TMP9]]
256 ; CHECK-NEXT: [[L_1:%.*]] = load i32, i32* [[T60]], align 4
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| /external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/ |
| D | bad-reduction.ll | 408 ; CHECK-NEXT: [[T60:%.*]] = zext i8 [[T59]] to i32
415 ; CHECK-NEXT: [[T61:%.*]] = shl nuw i32 [[T60]], 24
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | load-global-i16.ll | 3917 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T60.XYZW, T62.X, 0
4047 ; EG-NEXT: LSHR T60.W, T50.W, literal.y,
4051 ; EG-NEXT: AND_INT T60.Z, T50.W, literal.x,
4055 ; EG-NEXT: LSHR T60.Y, T50.Z, literal.y,
4057 ; EG-NEXT: AND_INT * T60.X, T50.Z, literal.z,
4101 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T60, T49.X
4222 ; CM-NEXT: LSHR * T60.W, T49.Y, literal.y,
4225 ; CM-NEXT: AND_INT T60.Z, T49.Y, literal.x,
4229 ; CM-NEXT: LSHR T60.Y, T49.X, literal.y,
4232 ; CM-NEXT: AND_INT T60.X, T49.X, literal.x,
[all …]
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| D | load-constant-i16.ll | 3456 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T60.XYZW, T50.X, 0
3585 ; EG-NEXT: LSHR T60.W, T50.Y, literal.y,
3589 ; EG-NEXT: AND_INT T60.Z, T50.Y, literal.x,
3593 ; EG-NEXT: LSHR T60.Y, T50.X, literal.y,
3595 ; EG-NEXT: AND_INT * T60.X, T50.X, literal.z,
4196 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T60.XYZW, T38.X, 0
4286 ; EG-NEXT: BFE_INT T60.Z, T42.W, 0.0, literal.x,
4290 ; EG-NEXT: BFE_INT T60.X, T42.Z, 0.0, literal.x,
4299 ; EG-NEXT: BFE_INT T60.W, T4.Y, 0.0, literal.x,
4303 ; EG-NEXT: BFE_INT T60.Y, PS, 0.0, literal.x,
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