1 #include <stdlib.h>
2 #include <sys/ioctl.h>
3 #include <stdio.h>
4 #include <string.h>
5 #include <assert.h>
6 #include <fcntl.h>
7 #include <inttypes.h>
8 #include <errno.h>
9 #include <sys/stat.h>
10 #include <sys/time.h>
11 #include "drm.h"
12 #include "i915_drm.h"
13 #include "drmtest.h"
14 #include "intel_bufmgr.h"
15 #include "intel_batchbuffer.h"
16 #include "intel_io.h"
17
18 #include "i830_reg.h"
19 #include "rendercopy.h"
20
21 #define TB0C_LAST_STAGE (1 << 31)
22 #define TB0C_RESULT_SCALE_1X (0 << 29)
23 #define TB0C_RESULT_SCALE_2X (1 << 29)
24 #define TB0C_RESULT_SCALE_4X (2 << 29)
25 #define TB0C_OP_ARG1 (1 << 25)
26 #define TB0C_OP_MODULE (3 << 25)
27 #define TB0C_OUTPUT_WRITE_CURRENT (0 << 24)
28 #define TB0C_OUTPUT_WRITE_ACCUM (1 << 24)
29 #define TB0C_ARG3_REPLICATE_ALPHA (1<<23)
30 #define TB0C_ARG3_INVERT (1<<22)
31 #define TB0C_ARG3_SEL_XXX
32 #define TB0C_ARG2_REPLICATE_ALPHA (1<<17)
33 #define TB0C_ARG2_INVERT (1<<16)
34 #define TB0C_ARG2_SEL_ONE (0 << 12)
35 #define TB0C_ARG2_SEL_FACTOR (1 << 12)
36 #define TB0C_ARG2_SEL_TEXEL0 (6 << 12)
37 #define TB0C_ARG2_SEL_TEXEL1 (7 << 12)
38 #define TB0C_ARG2_SEL_TEXEL2 (8 << 12)
39 #define TB0C_ARG2_SEL_TEXEL3 (9 << 12)
40 #define TB0C_ARG1_REPLICATE_ALPHA (1<<11)
41 #define TB0C_ARG1_INVERT (1<<10)
42 #define TB0C_ARG1_SEL_ONE (0 << 6)
43 #define TB0C_ARG1_SEL_TEXEL0 (6 << 6)
44 #define TB0C_ARG1_SEL_TEXEL1 (7 << 6)
45 #define TB0C_ARG1_SEL_TEXEL2 (8 << 6)
46 #define TB0C_ARG1_SEL_TEXEL3 (9 << 6)
47 #define TB0C_ARG0_REPLICATE_ALPHA (1<<5)
48 #define TB0C_ARG0_SEL_XXX
49
50 #define TB0A_CTR_STAGE_ENABLE (1<<31)
51 #define TB0A_RESULT_SCALE_1X (0 << 29)
52 #define TB0A_RESULT_SCALE_2X (1 << 29)
53 #define TB0A_RESULT_SCALE_4X (2 << 29)
54 #define TB0A_OP_ARG1 (1 << 25)
55 #define TB0A_OP_MODULE (3 << 25)
56 #define TB0A_OUTPUT_WRITE_CURRENT (0<<24)
57 #define TB0A_OUTPUT_WRITE_ACCUM (1<<24)
58 #define TB0A_CTR_STAGE_SEL_BITS_XXX
59 #define TB0A_ARG3_SEL_XXX
60 #define TB0A_ARG3_INVERT (1<<17)
61 #define TB0A_ARG2_INVERT (1<<16)
62 #define TB0A_ARG2_SEL_ONE (0 << 12)
63 #define TB0A_ARG2_SEL_TEXEL0 (6 << 12)
64 #define TB0A_ARG2_SEL_TEXEL1 (7 << 12)
65 #define TB0A_ARG2_SEL_TEXEL2 (8 << 12)
66 #define TB0A_ARG2_SEL_TEXEL3 (9 << 12)
67 #define TB0A_ARG1_INVERT (1<<10)
68 #define TB0A_ARG1_SEL_ONE (0 << 6)
69 #define TB0A_ARG1_SEL_TEXEL0 (6 << 6)
70 #define TB0A_ARG1_SEL_TEXEL1 (7 << 6)
71 #define TB0A_ARG1_SEL_TEXEL2 (8 << 6)
72 #define TB0A_ARG1_SEL_TEXEL3 (9 << 6)
73
74
gen2_emit_invariant(struct intel_batchbuffer * batch)75 static void gen2_emit_invariant(struct intel_batchbuffer *batch)
76 {
77 int i;
78
79 for (i = 0; i < 4; i++) {
80 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(i));
81 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | MAP_UNIT(i) |
82 DISABLE_TEX_STREAM_BUMP |
83 ENABLE_TEX_STREAM_COORD_SET | TEX_STREAM_COORD_SET(i) |
84 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(i));
85 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
86 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(i));
87 }
88
89 OUT_BATCH(_3DSTATE_MAP_COORD_SETBIND_CMD);
90 OUT_BATCH(TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) |
91 TEXBIND_SET2(TEXCOORDSRC_VTXSET_2) |
92 TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) |
93 TEXBIND_SET0(TEXCOORDSRC_VTXSET_0));
94
95 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
96
97 OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM);
98 OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
99
100 OUT_BATCH(_3DSTATE_W_STATE_CMD);
101 OUT_BATCH(MAGIC_W_STATE_DWORD1);
102 OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
103
104 OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD |
105 DISABLE_INDPT_ALPHA_BLEND |
106 ENABLE_ALPHA_BLENDFUNC | ABLENDFUNC_ADD);
107
108 OUT_BATCH(_3DSTATE_CONST_BLEND_COLOR_CMD);
109 OUT_BATCH(0);
110
111 OUT_BATCH(_3DSTATE_MODES_1_CMD |
112 ENABLE_COLR_BLND_FUNC | BLENDFUNC_ADD |
113 ENABLE_SRC_BLND_FACTOR | SRC_BLND_FACT(BLENDFACTOR_ONE) |
114 ENABLE_DST_BLND_FACTOR | DST_BLND_FACT(BLENDFACTOR_ZERO));
115
116 OUT_BATCH(_3DSTATE_ENABLES_1_CMD |
117 DISABLE_LOGIC_OP |
118 DISABLE_STENCIL_TEST |
119 DISABLE_DEPTH_BIAS |
120 DISABLE_SPEC_ADD |
121 DISABLE_FOG |
122 DISABLE_ALPHA_TEST |
123 DISABLE_DEPTH_TEST |
124 ENABLE_COLOR_BLEND);
125
126 OUT_BATCH(_3DSTATE_ENABLES_2_CMD |
127 DISABLE_STENCIL_WRITE |
128 DISABLE_DITHER |
129 DISABLE_DEPTH_WRITE |
130 ENABLE_COLOR_MASK |
131 ENABLE_COLOR_WRITE |
132 ENABLE_TEX_CACHE);
133 }
134
gen2_emit_target(struct intel_batchbuffer * batch,const struct igt_buf * dst)135 static void gen2_emit_target(struct intel_batchbuffer *batch,
136 const struct igt_buf *dst)
137 {
138 uint32_t tiling;
139 uint32_t format;
140
141 igt_assert_lte(dst->stride, 8192);
142 igt_assert_lte(igt_buf_width(dst), 2048);
143 igt_assert_lte(igt_buf_height(dst), 2048);
144
145 switch (dst->bpp) {
146 case 8: format = COLR_BUF_8BIT; break;
147 case 16: format = COLR_BUF_RGB565; break;
148 case 32: format = COLR_BUF_ARGB8888; break;
149 default: igt_assert(0);
150 }
151
152 tiling = 0;
153 if (dst->tiling != I915_TILING_NONE)
154 tiling = BUF_3D_TILED_SURFACE;
155 if (dst->tiling == I915_TILING_Y)
156 tiling |= BUF_3D_TILE_WALK_Y;
157
158 OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
159 OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling | BUF_3D_PITCH(dst->stride));
160 OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
161
162 OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
163 OUT_BATCH(format |
164 DSTORG_HORT_BIAS(0x8) |
165 DSTORG_VERT_BIAS(0x8));
166
167 OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
168 OUT_BATCH(0);
169 OUT_BATCH(0); /* ymin, xmin */
170 OUT_BATCH(DRAW_YMAX(igt_buf_height(dst) - 1) |
171 DRAW_XMAX(igt_buf_width(dst) - 1));
172 OUT_BATCH(0); /* yorig, xorig */
173 }
174
gen2_emit_texture(struct intel_batchbuffer * batch,const struct igt_buf * src,int unit)175 static void gen2_emit_texture(struct intel_batchbuffer *batch,
176 const struct igt_buf *src,
177 int unit)
178 {
179 uint32_t tiling;
180 uint32_t format;
181
182 igt_assert_lte(src->stride, 8192);
183 igt_assert_lte(igt_buf_width(src), 2048);
184 igt_assert_lte(igt_buf_height(src), 2048);
185
186 switch (src->bpp) {
187 case 8: format = MAPSURF_8BIT | MT_8BIT_L8; break;
188 case 16: format = MAPSURF_16BIT | MT_16BIT_RGB565; break;
189 case 32: format = MAPSURF_32BIT | MT_32BIT_ARGB8888; break;
190 default: igt_assert(0);
191 }
192
193 tiling = 0;
194 if (src->tiling != I915_TILING_NONE)
195 tiling = TM0S1_TILED_SURFACE;
196 if (src->tiling == I915_TILING_Y)
197 tiling |= TM0S1_TILE_WALK;
198
199 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 | LOAD_TEXTURE_MAP(unit) | 4);
200 OUT_RELOC(src->bo, I915_GEM_DOMAIN_SAMPLER, 0, 0);
201 OUT_BATCH((igt_buf_height(src) - 1) << TM0S1_HEIGHT_SHIFT |
202 (igt_buf_width(src) - 1) << TM0S1_WIDTH_SHIFT |
203 format | tiling);
204 OUT_BATCH((src->stride / 4 - 1) << TM0S2_PITCH_SHIFT | TM0S2_MAP_2D);
205 OUT_BATCH(FILTER_NEAREST << TM0S3_MAG_FILTER_SHIFT |
206 FILTER_NEAREST << TM0S3_MIN_FILTER_SHIFT |
207 MIPFILTER_NONE << TM0S3_MIP_FILTER_SHIFT);
208 OUT_BATCH(0); /* default color */
209
210 OUT_BATCH(_3DSTATE_MAP_COORD_SET_CMD | TEXCOORD_SET(unit) |
211 ENABLE_TEXCOORD_PARAMS | TEXCOORDS_ARE_NORMAL |
212 TEXCOORDTYPE_CARTESIAN |
213 ENABLE_ADDR_V_CNTL | TEXCOORD_ADDR_V_MODE(TEXCOORDMODE_CLAMP_BORDER) |
214 ENABLE_ADDR_U_CNTL | TEXCOORD_ADDR_U_MODE(TEXCOORDMODE_CLAMP_BORDER));
215 }
216
gen2_emit_copy_pipeline(struct intel_batchbuffer * batch)217 static void gen2_emit_copy_pipeline(struct intel_batchbuffer *batch)
218 {
219 OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD | DISABLE_INDPT_ALPHA_BLEND);
220 OUT_BATCH(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP |
221 DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS |
222 DISABLE_SPEC_ADD | DISABLE_FOG | DISABLE_ALPHA_TEST |
223 DISABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
224
225 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
226 LOAD_TEXTURE_BLEND_STAGE(0) | 1);
227 OUT_BATCH(TB0C_LAST_STAGE | TB0C_RESULT_SCALE_1X |
228 TB0C_OUTPUT_WRITE_CURRENT |
229 TB0C_OP_ARG1 | TB0C_ARG1_SEL_TEXEL0);
230 OUT_BATCH(TB0A_RESULT_SCALE_1X | TB0A_OUTPUT_WRITE_CURRENT |
231 TB0A_OP_ARG1 | TB0A_ARG1_SEL_TEXEL0);
232 }
233
gen2_render_copyfunc(struct intel_batchbuffer * batch,drm_intel_context * context,const struct igt_buf * src,unsigned src_x,unsigned src_y,unsigned width,unsigned height,const struct igt_buf * dst,unsigned dst_x,unsigned dst_y)234 void gen2_render_copyfunc(struct intel_batchbuffer *batch,
235 drm_intel_context *context,
236 const struct igt_buf *src, unsigned src_x, unsigned src_y,
237 unsigned width, unsigned height,
238 const struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
239 {
240 igt_assert(src->bpp == dst->bpp);
241
242 gen2_emit_invariant(batch);
243 gen2_emit_copy_pipeline(batch);
244
245 gen2_emit_target(batch, dst);
246 gen2_emit_texture(batch, src, 0);
247
248 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
249 I1_LOAD_S(2) | I1_LOAD_S(3) | I1_LOAD_S(8) | 2);
250 OUT_BATCH(1<<12);
251 OUT_BATCH(S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
252 OUT_BATCH(S8_ENABLE_COLOR_BUFFER_WRITE);
253
254 OUT_BATCH(_3DSTATE_VERTEX_FORMAT_2_CMD | TEXCOORDFMT_2D << 0);
255
256 OUT_BATCH(PRIM3D_INLINE | PRIM3D_RECTLIST | (3*4 -1));
257 emit_vertex(batch, dst_x + width);
258 emit_vertex(batch, dst_y + height);
259 emit_vertex_normalized(batch, src_x + width, igt_buf_width(src));
260 emit_vertex_normalized(batch, src_y + height, igt_buf_height(src));
261
262 emit_vertex(batch, dst_x);
263 emit_vertex(batch, dst_y + height);
264 emit_vertex_normalized(batch, src_x, igt_buf_width(src));
265 emit_vertex_normalized(batch, src_y + height, igt_buf_height(src));
266
267 emit_vertex(batch, dst_x);
268 emit_vertex(batch, dst_y);
269 emit_vertex_normalized(batch, src_x, igt_buf_width(src));
270 emit_vertex_normalized(batch, src_y, igt_buf_height(src));
271
272 intel_batchbuffer_flush(batch);
273 }
274