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Searched refs:TCS (Results 1 – 25 of 35) sorted by relevance

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/external/deqp/doc/testspecs/GLES31/
Dfunctional.tessellation.txt33 + Built-in inputs and outputs and basic data transfer between TCS and TES
34 - Read gl_PrimitiveID, gl_PatchVerticesIn in both TCS and TES
37 - Pass data in (gl_in/gl_out []) .gl_Position between VS, TCS and TES
49 from TCS to TES
94 either TCS or TES; the TCS cases pass the value as a "patch out" output to the
101 the value of a tessellation level in the TES gives the value set in the TCS. The
108 The barrier case uses both per-patch and per-vertex TCS output variables,
/external/mesa3d/docs/relnotes/
D18.3.5.rst96 - glsl/linker: Fix unmatched TCS outputs being reduced to local
134 - glsl: fix recording of variables for XFB in TCS shaders
148 - glsl/lower_vector_derefs: Don't use a temporary for TCS outputs
152 - glsl: TCS outputs can not be transform feedback candidates on GLES
D11.0.3.rst115 - radeonsi: handle fixed-func TCS shader create failure
116 - radeonsi: skip drawing if VS, TCS, TES, GS fail to compile or upload
D19.0.4.rst185 - radv: do not need to force emit the TCS regs on Vega20
190 - radv: only need to force emit the TCS regs on Vega10 and Raven1
D17.3.8.rst62 - anv/pipeline: fail if TCS/TES compile fail
D19.0.1.rst88 - glsl/lower_vector_derefs: Don't use a temporary for TCS outputs
D18.1.3.rst127 - radv: fix emitting the TCS regs on GFX9
D13.0.3.rst116 - radeonsi: wait for outstanding memory instructions in TCS barriers
D17.2.6.rst135 - i965: Make L3 configuration atom listen for TCS/TES program updates.
D20.0.3.rst179 - nir: fix packing of TCS varyings not read by the TES
D17.0.1.rst137 - mesa: Do (TCS && !TES) draw time validation in ES as well.
D18.0.1.rst83 - anv/pipeline: fail if TCS/TES compile fail
D12.0.2.rst272 - i965: Fix execution size of scalar TCS barrier setup code.
273 - i965: Fix barrier count shift in scalar TCS backend.
D13.0.4.rst170 - i965: Fix texturing in the vec4 TCS and GS backends.
D13.0.6.rst190 - mesa: Do (TCS && !TES) draw time validation in ES as well.
D11.0.0.rst239 gl_TessLevel\* writes have no effect for all but the last TCS
D20.1.0.rst2051 - r600/sfn: Add VS for TCS shader skeleton
4126 - nir: fix packing of TCS varyings not read by the TES
4164 - aco: Implement load_view_index for TCS and TES.
4191 - aco: Only write TCS outputs to LDS when they are read by the TCS.
4192 - aco: Don't store TCS outputs to LDS when we're sure that none are
4202 - aco: Allow combining TCS output VMEM stores.
4204 - aco: Skip 2nd read of merged wave info when TCS in/out vertices are
4216 - aco: Don't store LS VS outputs to LDS when TCS doesn't need them.
4233 - aco: Only store TCS outputs to VMEM when they are read by TES.
4238 - aco: Use 24-bit multiplication in TCS I/O
[all …]
D19.1.0.rst885 - iris: Add support for TCS passthrough
2031 - glsl: fix recording of variables for XFB in TCS shaders
2159 - glsl/lower_vector_derefs: Don't use a temporary for TCS outputs
2361 - glsl: TCS outputs can not be transform feedback candidates on GLES
2857 - iris: compile a TCS...don't bother with passthrough yet
2974 - iris: use 0 for TCS passthrough program string ID
3102 - iris: Fix TCS/TES slot unification
3148 - iris: Fix failed to compile TCS message
4386 - radv: do not need to force emit the TCS regs on Vega20
4392 - radv: only need to force emit the TCS regs on Vega10 and Raven1
D19.0.0.rst468 - glsl/linker: Fix unmatched TCS outputs being reduced to local
1206 - glsl: fix recording of variables for XFB in TCS shaders
1502 - glsl: TCS outputs can not be transform feedback candidates on GLES
1614 TCS.
1992 - radeonsi: show the fixed function TCS in debug dumps
D20.0.0.rst1683 - spirv: Add output memory semantics to OpControlBarrier in TCS
2011 - freedreno/ir3: Implement TCS synchronization intrinsics
2014 - freedreno/ir3: Pre-color TCS header and primitive ID inputs
2197 - st/mesa: print TCS/TES/GS/CS TGSI in the right place & keep disk
2270 - st/mesa: propagate gl_PatchVerticesIn from TCS to TES before linking
2284 - radeonsi/nir: fix location_frac handling for TCS outputs
/external/mesa3d/src/amd/compiler/
DREADME.md126 * TCS = Tessellation Control Shader, equivalent to D3D HS = Hull Shader
179 | with tess: | VS | TCS | | | TES | FS | `vertex_ls`, `tess_control_hs`, `…
181 | with both: | VS | TCS | TES | GS | GS copy| FS | `vertex_ls`, `tess_control_hs`, `…
192 | with tess: | VS + TCS | | TES | FS | `vertex_tess_control_hs`, `tess_e…
194 | with both: | VS + TCS | TES + GS | GS copy| FS | `vertex_tess_control_hs`, `tess_e…
204 | with tess: | VS + TCS | TES | FS | `vertex_tess_control_hs`, `tess_e…
206 | with both: | VS + TCS | TES + GS | FS | `vertex_tess_control_hs`, `tess_e…
Daco_ir.h1510 TCS = 1 << 2, /* Tessellation Control aka Hull Shader */ enumerator
1518 VS_TCS = VS | TCS,
1595 static constexpr Stage tess_control_hs(HWStage::HS, SWStage::TCS);
Daco_instruction_selection_setup.cpp1038 sw_stage = sw_stage | SWStage::TCS; in setup_isel_context()
1079 else if (sw_stage == SWStage::TCS) in setup_isel_context()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_pipe.c55 {"tcs", DBG(TCS), "Print tessellation control shaders"},
/external/mesa3d/docs/
Denvvars.rst333 ``INTEL_SCALAR_VS`` (or ``TCS``, ``TES``, ``GS``)

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