Home
last modified time | relevance | path

Searched refs:TEGRA_EVP_BASE (Results 1 – 4 of 4) sorted by relevance

/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/
Dplat_secondary.c62 mmio_write_32(TEGRA_EVP_BASE + EVP_CPU_RESET_VECTOR, in plat_secondary_setup()
64 val = mmio_read_32(TEGRA_EVP_BASE + EVP_CPU_RESET_VECTOR); in plat_secondary_setup()
/external/arm-trusted-firmware/plat/nvidia/tegra/drivers/flowctrl/
Dflowctrl.c271 mmio_write_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR, entrypoint); in tegra_fc_bpmp_on()
272 while (entrypoint != mmio_read_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR)) in tegra_fc_bpmp_on()
297 mmio_write_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR, 0); in tegra_fc_bpmp_off()
298 while (0 != mmio_read_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR)) in tegra_fc_bpmp_off()
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t132/
Dtegra_def.h73 #define TEGRA_EVP_BASE U(0x6000F000) macro
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t210/
Dtegra_def.h185 #define TEGRA_EVP_BASE U(0x6000F000) macro