/external/llvm/include/llvm/CodeGen/ |
D | LivePhysRegs.h | 44 const TargetRegisterInfo *TRI; variable 51 LivePhysRegs() : TRI(nullptr), LiveRegs() {} in LivePhysRegs() 54 LivePhysRegs(const TargetRegisterInfo *TRI) : TRI(TRI) { in LivePhysRegs() argument 55 assert(TRI && "Invalid TargetRegisterInfo pointer."); in LivePhysRegs() 56 LiveRegs.setUniverse(TRI->getNumRegs()); in LivePhysRegs() 60 void init(const TargetRegisterInfo *TRI) { in init() argument 61 assert(TRI && "Invalid TargetRegisterInfo pointer."); in init() 62 this->TRI = TRI; in init() 64 LiveRegs.setUniverse(TRI->getNumRegs()); in init() 75 assert(TRI && "LivePhysRegs is not initialized."); in addReg() [all …]
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/external/llvm/lib/Target/AMDGPU/ |
D | SIFixSGPRCopies.cpp | 115 static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) { in hasVGPROperands() argument 122 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands() 130 const SIRegisterInfo &TRI, in getCopyRegClasses() argument 138 TRI.getPhysRegClass(SrcReg); in getCopyRegClasses() 146 TRI.getPhysRegClass(DstReg); in getCopyRegClasses() 153 const SIRegisterInfo &TRI) { in isVGPRToSGPRCopy() argument 154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC); in isVGPRToSGPRCopy() 159 const SIRegisterInfo &TRI) { in isSGPRToVGPRCopy() argument 160 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC); in isSGPRToVGPRCopy() 177 const SIRegisterInfo *TRI, in foldVGPRCopyIntoRegSequence() argument [all …]
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D | SIFrameLowering.cpp | 64 const SIRegisterInfo *TRI = &TII->getRegisterInfo(); in emitPrologue() local 75 unsigned PreloadedScratchWaveOffsetReg = TRI->getPreloadedValue( in emitPrologue() 80 PreloadedPrivateBufferReg = TRI->getPreloadedValue( in emitPrologue() 100 = TRI->getPreloadedValue(MF, SIRegisterInfo::FLAT_SCRATCH_INIT); in emitPrologue() 106 unsigned FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitPrologue() 110 unsigned FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitPrologue() 155 if (ScratchRsrcReg == TRI->reservedPrivateSegmentBufferReg(MF)) { in emitPrologue() 174 if (ScratchWaveOffsetReg == TRI->reservedPrivateSegmentWaveByteOffsetReg(MF)) { in emitPrologue() 196 TRI->isSubRegisterEq(ScratchRsrcReg, Reg)) in emitPrologue() 209 assert(!TRI->isSubRegister(ScratchRsrcReg, ScratchWaveOffsetReg)); in emitPrologue() [all …]
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/external/llvm-project/llvm/lib/CodeGen/ |
D | MachineCopyPropagation.cpp | 101 const TargetRegisterInfo &TRI) { in markRegsUnavailable() argument 104 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) { in markRegsUnavailable() 113 void invalidateRegister(MCRegister Reg, const TargetRegisterInfo &TRI) { in invalidateRegister() argument 119 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) { in invalidateRegister() 131 for (MCRegUnitIterator RUI(InvalidReg, &TRI); RUI.isValid(); ++RUI) in invalidateRegister() 136 void clobberRegister(MCRegister Reg, const TargetRegisterInfo &TRI) { in clobberRegister() argument 137 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) { in clobberRegister() 142 markRegsUnavailable(I->second.DefRegs, TRI); in clobberRegister() 146 markRegsUnavailable({MI->getOperand(0).getReg().asMCReg()}, TRI); in clobberRegister() 154 void trackCopy(MachineInstr *MI, const TargetRegisterInfo &TRI) { in trackCopy() argument [all …]
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D | RegisterClassInfo.cpp | 48 if (MF->getSubtarget().getRegisterInfo() != TRI) { in runOnMachineFunction() 49 TRI = MF->getSubtarget().getRegisterInfo(); in runOnMachineFunction() 50 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction() 55 assert(TRI && "no register info set"); in runOnMachineFunction() 62 CalleeSavedAliases.assign(TRI->getNumRegs(), 0); in runOnMachineFunction() 64 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) in runOnMachineFunction() 80 unsigned NumPSets = TRI->getNumRegPressureSets(); in runOnMachineFunction() 115 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute() 135 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute() 148 TRI->getLargestLegalSuperClass(RC, *MF)) in compute() [all …]
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D | LiveRegMatrix.cpp | 56 TRI = MF.getSubtarget().getRegisterInfo(); in runOnMachineFunction() 60 unsigned NumRegUnits = TRI->getNumRegUnits(); in runOnMachineFunction() 80 static bool foreachUnit(const TargetRegisterInfo *TRI, in foreachUnit() argument 84 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit() 96 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit() 105 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg(), TRI) << " to " in assign() 106 << printReg(PhysReg, TRI) << ':'); in assign() 111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { in assign() 112 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range); in assign() 123 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg(), TRI) in unassign() [all …]
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D | FixupStatepointCallerSaved.cpp | 96 static unsigned getRegisterSize(const TargetRegisterInfo &TRI, Register Reg) { in getRegisterSize() argument 97 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in getRegisterSize() 98 return TRI.getSpillSize(*RC); in getRegisterSize() 117 const TargetRegisterInfo &TRI) { in performCopyPropagation() argument 119 int Idx = RI->findRegisterUseOperandIdx(Reg, false, &TRI); in performCopyPropagation() 132 if (It->readsRegister(Reg, &TRI) && !Use) in performCopyPropagation() 134 if (It->modifiesRegister(Reg, &TRI)) { in performCopyPropagation() 149 if (getRegisterSize(TRI, Reg) != getRegisterSize(TRI, SrcReg)) in performCopyPropagation() 153 << printReg(Reg, &TRI) << " -> " << printReg(SrcReg, &TRI) in performCopyPropagation() 210 const TargetRegisterInfo &TRI; member in __anon6a7383e10211::FrameIndexesCache [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
D | MachineCopyPropagation.cpp | 100 const TargetRegisterInfo &TRI) { in markRegsUnavailable() argument 103 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) { in markRegsUnavailable() 112 void invalidateRegister(unsigned Reg, const TargetRegisterInfo &TRI) { in invalidateRegister() argument 117 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) { in invalidateRegister() 129 for (MCRegUnitIterator RUI(InvalidReg, &TRI); RUI.isValid(); ++RUI) in invalidateRegister() 134 void clobberRegister(unsigned Reg, const TargetRegisterInfo &TRI) { in clobberRegister() argument 135 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) { in clobberRegister() 140 markRegsUnavailable(I->second.DefRegs, TRI); in clobberRegister() 144 markRegsUnavailable({MI->getOperand(0).getReg()}, TRI); in clobberRegister() 152 void trackCopy(MachineInstr *MI, const TargetRegisterInfo &TRI) { in trackCopy() argument [all …]
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D | RegisterClassInfo.cpp | 48 if (MF->getSubtarget().getRegisterInfo() != TRI) { in runOnMachineFunction() 49 TRI = MF->getSubtarget().getRegisterInfo(); in runOnMachineFunction() 50 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction() 55 assert(TRI && "no register info set"); in runOnMachineFunction() 62 CalleeSavedAliases.assign(TRI->getNumRegs(), 0); in runOnMachineFunction() 64 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) in runOnMachineFunction() 80 unsigned NumPSets = TRI->getNumRegPressureSets(); in runOnMachineFunction() 115 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute() 135 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute() 148 TRI->getLargestLegalSuperClass(RC, *MF)) in compute() [all …]
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D | LiveRegMatrix.cpp | 56 TRI = MF.getSubtarget().getRegisterInfo(); in runOnMachineFunction() 60 unsigned NumRegUnits = TRI->getNumRegUnits(); in runOnMachineFunction() 80 static bool foreachUnit(const TargetRegisterInfo *TRI, in foreachUnit() argument 84 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit() 96 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit() 105 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI) << " to " in assign() 106 << printReg(PhysReg, TRI) << ':'); in assign() 111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { in assign() 112 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range); in assign() 123 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI) << " from " in unassign() [all …]
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D | TargetRegisterInfo.cpp | 89 Printable printReg(Register Reg, const TargetRegisterInfo *TRI, in printReg() argument 91 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) { in printReg() 103 } else if (!TRI) in printReg() 105 else if (Reg < TRI->getNumRegs()) { in printReg() 107 printLowerCase(TRI->getName(Reg), OS); in printReg() 112 if (TRI) in printReg() 113 OS << ':' << TRI->getSubRegIndexName(SubIdx); in printReg() 120 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { in printRegUnit() argument 121 return Printable([Unit, TRI](raw_ostream &OS) { in printRegUnit() 123 if (!TRI) { in printRegUnit() [all …]
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/external/llvm/lib/CodeGen/ |
D | RegisterClassInfo.cpp | 33 : Tag(0), MF(nullptr), TRI(nullptr), CalleeSaved(nullptr) {} in RegisterClassInfo() 40 if (MF->getSubtarget().getRegisterInfo() != TRI) { in runOnMachineFunction() 41 TRI = MF->getSubtarget().getRegisterInfo(); in runOnMachineFunction() 42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction() 43 unsigned NumPSets = TRI->getNumRegPressureSets(); in runOnMachineFunction() 50 assert(TRI && "no register info set"); in runOnMachineFunction() 51 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); in runOnMachineFunction() 56 CSRNum.resize(TRI->getNumRegs(), 0); in runOnMachineFunction() 58 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) in runOnMachineFunction() 103 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute() [all …]
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D | TargetRegisterInfo.cpp | 45 Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI, in PrintReg() argument 47 return Printable([Reg, TRI, SubIdx](raw_ostream &OS) { in PrintReg() 54 else if (TRI && Reg < TRI->getNumRegs()) in PrintReg() 55 OS << '%' << TRI->getName(Reg); in PrintReg() 59 if (TRI) in PrintReg() 60 OS << ':' << TRI->getSubRegIndexName(SubIdx); in PrintReg() 67 Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { in PrintRegUnit() argument 68 return Printable([Unit, TRI](raw_ostream &OS) { in PrintRegUnit() 70 if (!TRI) { in PrintRegUnit() 76 if (Unit >= TRI->getNumRegUnits()) { in PrintRegUnit() [all …]
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D | LiveRegMatrix.cpp | 50 TRI = MF.getSubtarget().getRegisterInfo(); in runOnMachineFunction() 54 unsigned NumRegUnits = TRI->getNumRegUnits(); in runOnMachineFunction() 74 bool foreachUnit(const TargetRegisterInfo *TRI, LiveInterval &VRegInterval, in foreachUnit() argument 77 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit() 89 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit() 98 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) in assign() 99 << " to " << PrintReg(PhysReg, TRI) << ':'); in assign() 103 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, in assign() 105 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << ' ' << Range); in assign() 116 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) in unassign() [all …]
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/external/llvm/lib/CodeGen/AsmPrinter/ |
D | DwarfExpression.cpp | 68 bool DwarfExpression::AddMachineRegIndirect(const TargetRegisterInfo &TRI, in AddMachineRegIndirect() argument 70 if (isFrameRegister(TRI, MachineReg)) { in AddMachineRegIndirect() 77 int DwarfReg = TRI.getDwarfRegNum(MachineReg, false); in AddMachineRegIndirect() 85 bool DwarfExpression::AddMachineRegPiece(const TargetRegisterInfo &TRI, in AddMachineRegPiece() argument 89 if (!TRI.isPhysicalRegister(MachineReg)) in AddMachineRegPiece() 92 int Reg = TRI.getDwarfRegNum(MachineReg, false); in AddMachineRegPiece() 104 for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) { in AddMachineRegPiece() 105 Reg = TRI.getDwarfRegNum(*SR, false); in AddMachineRegPiece() 107 unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg); in AddMachineRegPiece() 108 unsigned Size = TRI.getSubRegIdxSize(Idx); in AddMachineRegPiece() [all …]
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/external/llvm/lib/CodeGen/GlobalISel/ |
D | RegisterBank.cpp | 24 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const { in verify() 26 assert(ContainedRegClasses.size() == TRI.getNumRegClasses() && in verify() 28 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) { in verify() 29 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify() 40 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify() 75 void RegisterBank::dump(const TargetRegisterInfo *TRI) const { in dump() 76 print(dbgs(), /* IsForDebug */ true, TRI); in dump() 80 const TargetRegisterInfo *TRI) const { in print() 90 if (!TRI || ContainedRegClasses.empty()) in print() 92 assert(ContainedRegClasses.size() == TRI->getNumRegClasses() && in print() [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
D | LivePhysRegs.h | 49 const TargetRegisterInfo *TRI = nullptr; variable 58 LivePhysRegs(const TargetRegisterInfo &TRI) : TRI(&TRI) { in LivePhysRegs() argument 59 LiveRegs.setUniverse(TRI.getNumRegs()); in LivePhysRegs() 66 void init(const TargetRegisterInfo &TRI) { in init() argument 67 this->TRI = &TRI; in init() 69 LiveRegs.setUniverse(TRI.getNumRegs()); in init() 80 assert(TRI && "LivePhysRegs is not initialized."); in addReg() 81 assert(Reg <= TRI->getNumRegs() && "Expected a physical register."); in addReg() 82 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in addReg() 90 assert(TRI && "LivePhysRegs is not initialized."); in removeReg() [all …]
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D | LiveRegUnits.h | 31 const TargetRegisterInfo *TRI = nullptr; variable 39 LiveRegUnits(const TargetRegisterInfo &TRI) { in LiveRegUnits() argument 40 init(TRI); in LiveRegUnits() 50 const TargetRegisterInfo *TRI) { in accumulateUsedDefed() argument 63 if (!TRI->isConstantPhysReg(Reg)) in accumulateUsedDefed() 74 void init(const TargetRegisterInfo &TRI) { in init() argument 75 this->TRI = &TRI; in init() 77 Units.resize(TRI.getNumRegUnits()); in init() 88 for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) in addReg() 95 for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) { in addRegMasked() [all …]
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/external/llvm-project/llvm/include/llvm/CodeGen/ |
D | LivePhysRegs.h | 49 const TargetRegisterInfo *TRI = nullptr; variable 58 LivePhysRegs(const TargetRegisterInfo &TRI) : TRI(&TRI) { in LivePhysRegs() argument 59 LiveRegs.setUniverse(TRI.getNumRegs()); in LivePhysRegs() 66 void init(const TargetRegisterInfo &TRI) { in init() argument 67 this->TRI = &TRI; in init() 69 LiveRegs.setUniverse(TRI.getNumRegs()); in init() 80 assert(TRI && "LivePhysRegs is not initialized."); in addReg() 81 assert(Reg <= TRI->getNumRegs() && "Expected a physical register."); in addReg() 82 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in addReg() 90 assert(TRI && "LivePhysRegs is not initialized."); in removeReg() [all …]
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D | LiveRegUnits.h | 31 const TargetRegisterInfo *TRI = nullptr; variable 39 LiveRegUnits(const TargetRegisterInfo &TRI) { in LiveRegUnits() argument 40 init(TRI); in LiveRegUnits() 50 const TargetRegisterInfo *TRI) { in accumulateUsedDefed() argument 63 if (!TRI->isConstantPhysReg(Reg)) in accumulateUsedDefed() 74 void init(const TargetRegisterInfo &TRI) { in init() argument 75 this->TRI = &TRI; in init() 77 Units.resize(TRI.getNumRegUnits()); in init() 88 for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) in addReg() 95 for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) { in addRegMasked() [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
D | RegisterBank.cpp | 31 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const { in verify() 33 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) { in verify() 34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify() 45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify() 52 assert(getSize() >= TRI.getRegSizeInBits(SubRC) && in verify() 81 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const { in dump() 82 print(dbgs(), /* IsForDebug */ true, TRI); in dump() 87 const TargetRegisterInfo *TRI) const { in print() 97 if (!TRI || ContainedRegClasses.empty()) in print() 99 assert(ContainedRegClasses.size() == TRI->getNumRegClasses() && in print() [all …]
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/external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
D | RegisterBank.cpp | 31 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const { in verify() 33 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) { in verify() 34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify() 45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify() 52 assert(getSize() >= TRI.getRegSizeInBits(SubRC) && in verify() 81 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const { in dump() 82 print(dbgs(), /* IsForDebug */ true, TRI); in dump() 87 const TargetRegisterInfo *TRI) const { in print() 97 if (!TRI || ContainedRegClasses.empty()) in print() 99 assert(ContainedRegClasses.size() == TRI->getNumRegClasses() && in print() [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIFixSGPRCopies.cpp | 118 const SIRegisterInfo *TRI; member in __anone749b4990111::SIFixSGPRCopies 154 const SIRegisterInfo *TRI) { in hasVectorOperands() argument 161 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVectorOperands() 169 const SIRegisterInfo &TRI, in getCopyRegClasses() argument 176 : TRI.getPhysRegClass(SrcReg); in getCopyRegClasses() 183 : TRI.getPhysRegClass(DstReg); in getCopyRegClasses() 190 const SIRegisterInfo &TRI) { in isVGPRToSGPRCopy() argument 191 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) && in isVGPRToSGPRCopy() 192 TRI.hasVectorRegisters(SrcRC); in isVGPRToSGPRCopy() 197 const SIRegisterInfo &TRI) { in isSGPRToVGPRCopy() argument [all …]
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/external/llvm-project/llvm/lib/Target/AMDGPU/ |
D | SIFixSGPRCopies.cpp | 118 const SIRegisterInfo *TRI; member in __anon7d07f3050111::SIFixSGPRCopies 154 const SIRegisterInfo *TRI) { in hasVectorOperands() argument 160 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVectorOperands() 168 const SIRegisterInfo &TRI, in getCopyRegClasses() argument 175 : TRI.getPhysRegClass(SrcReg); in getCopyRegClasses() 182 : TRI.getPhysRegClass(DstReg); in getCopyRegClasses() 189 const SIRegisterInfo &TRI) { in isVGPRToSGPRCopy() argument 190 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) && in isVGPRToSGPRCopy() 191 TRI.hasVectorRegisters(SrcRC); in isVGPRToSGPRCopy() 196 const SIRegisterInfo &TRI) { in isSGPRToVGPRCopy() argument [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | MipsOptionRecord.h | 46 const MCRegisterInfo *TRI = Context.getRegisterInfo(); in MipsRegInfoRecord() local 47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord() 48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord() 49 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord() 50 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord() 51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord() 52 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); in MipsRegInfoRecord() 53 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); in MipsRegInfoRecord() 54 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); in MipsRegInfoRecord() 55 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); in MipsRegInfoRecord()
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