/external/llvm-project/llvm/lib/Target/PowerPC/ |
D | PPCInstrHTM.td | 64 def TSR : XForm_htm2 <31, 750, 128 (TSR (HTM_get_imm imm:$L))>; 161 (TSR 1)>; 164 (TSR 0)>; 174 def : InstAlias<"tsuspend.", (TSR 0)>, Requires<[HasHTM]>; 175 def : InstAlias<"tresume.", (TSR 1)>, Requires<[HasHTM]>;
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D | P9InstrResources.td | 198 TSR,
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
D | PPCInstrHTM.td | 64 def TSR : XForm_htm2 <31, 750, 128 (TSR (HTM_get_imm imm:$L))>; 161 (TSR 1)>; 164 (TSR 0)>;
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D | P9InstrResources.td | 198 TSR,
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/external/llvm/lib/Target/PowerPC/ |
D | PPCInstrHTM.td | 63 def TSR : XForm_htm2 <31, 750, 131 (TSR (HTM_get_imm imm:$L))>; 164 (TSR 1)>; 167 (TSR 0)>;
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/external/llvm-project/llvm/lib/Target/Hexagon/ |
D | HexagonEarlyIfConv.cpp | 204 unsigned TSR, unsigned FR, unsigned FSR); 779 unsigned PredR, unsigned TR, unsigned TSR, unsigned FR, unsigned FSR) { in buildMux() argument 805 .addReg(TR, 0, TSR) in buildMux() 818 unsigned TR = 0, TSR = 0, FR = 0, FSR = 0, SR = 0, SSR = 0; in updatePhiNodes() local 824 TR = RO.getReg(), TSR = RO.getSubReg(); in updatePhiNodes() 833 TR = SR, TSR = SSR; in updatePhiNodes() 844 FP.PredR, TR, TSR, FR, FSR); in updatePhiNodes() 847 MuxSR = TSR; in updatePhiNodes()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
D | HexagonEarlyIfConv.cpp | 204 unsigned TSR, unsigned FR, unsigned FSR); 779 unsigned PredR, unsigned TR, unsigned TSR, unsigned FR, unsigned FSR) { in buildMux() argument 805 .addReg(TR, 0, TSR) in buildMux() 818 unsigned TR = 0, TSR = 0, FR = 0, FSR = 0, SR = 0, SSR = 0; in updatePhiNodes() local 824 TR = RO.getReg(), TSR = RO.getSubReg(); in updatePhiNodes() 833 TR = SR, TSR = SSR; in updatePhiNodes() 844 FP.PredR, TR, TSR, FR, FSR); in updatePhiNodes() 847 MuxSR = TSR; in updatePhiNodes()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonEarlyIfConv.cpp | 781 unsigned TR = 0, TSR = 0, FR = 0, FSR = 0, SR = 0, SSR = 0; in updatePhiNodes() local 787 TR = RO.getReg(), TSR = RO.getSubReg(); in updatePhiNodes() 796 TR = SR, TSR = SSR; in updatePhiNodes() 814 .addReg(TR, 0, TSR) in updatePhiNodes()
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
D | PPCGenMCCodeEmitter.inc | 1736 UINT64_C(2080376285), // TSR 3713 case PPC::TSR: { 8146 CEFBS_None, // TSR = 1723
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D | PPCGenAsmWriter.inc | 3391 263685U, // TSR 5682 0U, // TSR 6346 // RFEBB, TBEGIN, TEND, TSR
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D | PPCGenDisassemblerTables.inc | 1614 /* 7360 */ MCD::OPC_Decode, 187, 13, 73, // Opcode: TSR
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D | PPCGenInstrInfo.inc | 1738 TSR = 1723, 4707 …eledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo2, -1 ,nullptr }, // Inst #1723 = TSR
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D | PPCGenAsmMatcher.inc | 6477 { 10273 /* tsr */, PPC::TSR, Convert__U1Imm1_1, AMFBS_None, { MCK__DOT_, MCK_U1Imm }, },
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D | PPCGenDAGISel.inc | 24693 /* 59720*/ OPC_MorphNodeTo1, TARGET_VAL(PPC::TSR), 0|OPFL_Chain, 24696 // Dst: (TSR:{ *:[i32] } (HTM_get_imm:{ *:[i32] } (imm:{ *:[i32] }):$L)) 24747 /* 59826*/ OPC_MorphNodeTo1, TARGET_VAL(PPC::TSR), 0|OPFL_Chain, 24750 // Dst: (TSR:{ *:[i32] } 1:{ *:[i32] }) 24756 /* 59843*/ OPC_MorphNodeTo1, TARGET_VAL(PPC::TSR), 0|OPFL_Chain, 24759 // Dst: (TSR:{ *:[i32] } 0:{ *:[i32] })
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/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ |
D | stm32l476xx.h | 287 …__IO uint32_t TSR; /*!< CAN transmit status register, Address … member
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/external/cldr/tools/java/org/unicode/cldr/util/data/external/ |
D | 2013-1_UNLOCODE_CodeListPart3.csv | 4370 ,"RO","TSR","Timisoara","Timisoara",,"---4----","AI","9601",,, 7072 ,"SE","TSR","Torsaker","Torsaker","Y","--3-----","RL","0701",,"6304N 01744E", 22048 ,"US","TSR","Petersburg","Petersburg","TN","--3-----","RL","0701",,"3624N 08258W",
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D | 2013-1_UNLOCODE_CodeListPart2.csv | 17346 ,"JP","TSR","Tsuruoka","Tsuruoka","06","--3-----","RQ","0907",,"3843N 13949E", 20211 ,"MY","TSR","Tanjong Surat","Tanjong Surat",,"1-------","QQ","8103",,,
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D | 2013-1_UNLOCODE_CodeListPart1.csv | 33458 ,"FR","TSR","Borest","Borest",,"--3-----","RL","0901",,,
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/external/toolchain-utils/android_bench_suite/panorama_input/ |
D | test_034.ppm | 2088 …�ʷ�ɽ�ϑ��#'4*,6./:45=56>446003/-0.,/-*.*(,(&)'%(%%'&&(&&('')***,,,/.-431:87TSR^[_(&)"=BO��о��…
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D | test_008.ppm | 110 #*%,#"/,(A=:;74ROK���TSR)& (%?.-?.-J'.eBI> #3
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