/external/tpm2-tss/src/tss2-esys/api/ |
D | Esys_Startup.c | 71 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_Startup() 74 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_Startup() 183 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_Startup_Finish()
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D | Esys_FlushContext.c | 82 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_FlushContext() 85 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_FlushContext() 205 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_FlushContext_Finish()
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D | Esys_StirRandom.c | 85 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_StirRandom() 88 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_StirRandom() 234 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_StirRandom_Finish()
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D | Esys_TestParms.c | 88 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_TestParms() 91 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_TestParms() 240 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_TestParms_Finish()
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D | Esys_Shutdown.c | 88 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_Shutdown() 91 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_Shutdown() 240 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_Shutdown_Finish()
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D | Esys_SelfTest.c | 88 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_SelfTest() 91 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_SelfTest() 240 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_SelfTest_Finish()
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D | Esys_PolicyPhysicalPresence.c | 91 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_PolicyPhysicalPresence() 94 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_PolicyPhysicalPresence() 254 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_PolicyPhysicalPresence_Finish()
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D | Esys_PolicyRestart.c | 91 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_PolicyRestart() 94 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_PolicyRestart() 253 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_PolicyRestart_Finish()
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D | Esys_ReadClock.c | 88 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_ReadClock() 91 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_ReadClock() 249 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_ReadClock_Finish()
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D | Esys_ChangeEPS.c | 91 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_ChangeEPS() 94 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_ChangeEPS() 258 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_ChangeEPS_Finish()
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D | Esys_ContextLoad.c | 86 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_ContextLoad() 89 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_ContextLoad() 250 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_ContextLoad_Finish()
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D | Esys_EC_Ephemeral.c | 91 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_EC_Ephemeral() 94 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_EC_Ephemeral() 254 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_EC_Ephemeral_Finish()
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D | Esys_PolicyAuthorize.c | 101 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_PolicyAuthorize() 104 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_PolicyAuthorize() 277 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_PolicyAuthorize_Finish()
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D | Esys_PolicyPCR.c | 93 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_PolicyPCR() 96 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_PolicyPCR() 259 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_PolicyPCR_Finish()
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D | Esys_Clear.c | 90 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_Clear() 93 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_Clear() 262 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_Clear_Finish()
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D | Esys_ContextSave.c | 85 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_ContextSave() 88 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_ContextSave() 218 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_ContextSave_Finish()
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D | Esys_DictionaryAttackLockReset.c | 91 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_DictionaryAttackLockReset() 94 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_DictionaryAttackLockReset() 259 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_DictionaryAttackLockReset_Finish()
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D | Esys_FirmwareRead.c | 89 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_FirmwareRead() 92 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_FirmwareRead() 250 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_FirmwareRead_Finish()
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D | Esys_ClockRateAdjust.c | 93 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_ClockRateAdjust() 96 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_ClockRateAdjust() 262 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_ClockRateAdjust_Finish()
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D | Esys_ECC_Parameters.c | 91 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_ECC_Parameters() 94 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_ECC_Parameters() 254 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_ECC_Parameters_Finish()
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D | Esys_IncrementalSelfTest.c | 91 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_IncrementalSelfTest() 94 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_IncrementalSelfTest() 254 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_IncrementalSelfTest_Finish()
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D | Esys_PCR_Extend.c | 93 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_PCR_Extend() 96 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_PCR_Extend() 262 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_PCR_Extend_Finish()
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D | Esys_PolicyCpHash.c | 93 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_PolicyCpHash() 96 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_PolicyCpHash() 258 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_PolicyCpHash_Finish()
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D | Esys_PolicyGetDigest.c | 92 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) in Esys_PolicyGetDigest() 95 } while ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN); in Esys_PolicyGetDigest() 264 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { in Esys_PolicyGetDigest_Finish()
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/external/tpm2-tss/src/tss2-fapi/ |
D | ifapi_macros.h | 51 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) \ 59 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) \ 100 if ((r & ~TSS2_RC_LAYER_MASK) == TSS2_BASE_RC_TRY_AGAIN) { \
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