1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/i810/i810_reg.h,v 1.13 2003/02/06 04:18:04 dawes Exp $ */ 2 /************************************************************************** 3 4 Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. 5 All Rights Reserved. 6 7 Permission is hereby granted, free of charge, to any person obtaining a 8 copy of this software and associated documentation files (the 9 "Software"), to deal in the Software without restriction, including 10 without limitation the rights to use, copy, modify, merge, publish, 11 distribute, sub license, and/or sell copies of the Software, and to 12 permit persons to whom the Software is furnished to do so, subject to 13 the following conditions: 14 15 The above copyright notice and this permission notice (including the 16 next paragraph) shall be included in all copies or substantial portions 17 of the Software. 18 19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 23 ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 27 **************************************************************************/ 28 29 /* @file 30 * Register names and fields for Intel graphics. 31 */ 32 33 /* 34 * Authors: 35 * Keith Whitwell <keith@tungstengraphics.com> 36 * Eric Anholt <eric@anholt.net> 37 * 38 * based on the i740 driver by 39 * Kevin E. Martin <kevin@precisioninsight.com> 40 * 41 * 42 */ 43 44 #ifndef _I810_REG_H 45 #define _I810_REG_H 46 47 /* I/O register offsets 48 */ 49 #define SRX 0x3C4 /* p208 */ 50 #define GRX 0x3CE /* p213 */ 51 #define ARX 0x3C0 /* p224 */ 52 53 /* VGA Color Palette Registers */ 54 #define DACMASK 0x3C6 /* p232 */ 55 #define DACSTATE 0x3C7 /* p232 */ 56 #define DACRX 0x3C7 /* p233 */ 57 #define DACWX 0x3C8 /* p233 */ 58 #define DACDATA 0x3C9 /* p233 */ 59 60 /* CRT Controller Registers (CRX) */ 61 #define START_ADDR_HI 0x0C /* p246 */ 62 #define START_ADDR_LO 0x0D /* p247 */ 63 #define VERT_SYNC_END 0x11 /* p249 */ 64 #define EXT_VERT_TOTAL 0x30 /* p257 */ 65 #define EXT_VERT_DISPLAY 0x31 /* p258 */ 66 #define EXT_VERT_SYNC_START 0x32 /* p259 */ 67 #define EXT_VERT_BLANK_START 0x33 /* p260 */ 68 #define EXT_HORIZ_TOTAL 0x35 /* p261 */ 69 #define EXT_HORIZ_BLANK 0x39 /* p261 */ 70 #define EXT_START_ADDR 0x40 /* p262 */ 71 #define EXT_START_ADDR_ENABLE 0x80 72 #define EXT_OFFSET 0x41 /* p263 */ 73 #define EXT_START_ADDR_HI 0x42 /* p263 */ 74 #define INTERLACE_CNTL 0x70 /* p264 */ 75 #define INTERLACE_ENABLE 0x80 76 #define INTERLACE_DISABLE 0x00 77 78 /* Miscellaneous Output Register 79 */ 80 #define MSR_R 0x3CC /* p207 */ 81 #define MSR_W 0x3C2 /* p207 */ 82 #define IO_ADDR_SELECT 0x01 83 84 #define MDA_BASE 0x3B0 /* p207 */ 85 #define CGA_BASE 0x3D0 /* p207 */ 86 87 /* CR80 - IO Control, p264 88 */ 89 #define IO_CTNL 0x80 90 #define EXTENDED_ATTR_CNTL 0x02 91 #define EXTENDED_CRTC_CNTL 0x01 92 93 /* GR10 - Address mapping, p221 94 */ 95 #define ADDRESS_MAPPING 0x10 96 #define PAGE_TO_LOCAL_MEM_ENABLE 0x10 97 #define GTT_MEM_MAP_ENABLE 0x08 98 #define PACKED_MODE_ENABLE 0x04 99 #define LINEAR_MODE_ENABLE 0x02 100 #define PAGE_MAPPING_ENABLE 0x01 101 102 #define HOTKEY_VBIOS_SWITCH_BLOCK 0x80 103 #define HOTKEY_SWITCH 0x20 104 #define HOTKEY_TOGGLE 0x10 105 106 /* Blitter control, p378 107 */ 108 #define BITBLT_CNTL 0x7000c 109 #define COLEXP_MODE 0x30 110 #define COLEXP_8BPP 0x00 111 #define COLEXP_16BPP 0x10 112 #define COLEXP_24BPP 0x20 113 #define COLEXP_RESERVED 0x30 114 #define BITBLT_STATUS 0x01 115 116 #define CHDECMISC 0x10111 117 #define DCC 0x10200 118 #define C0DRB0 0x10200 119 #define C0DRB1 0x10202 120 #define C0DRB2 0x10204 121 #define C0DRB3 0x10206 122 #define C0DRA01 0x10208 123 #define C0DRA23 0x1020a 124 #define C1DRB0 0x10600 125 #define C1DRB1 0x10602 126 #define C1DRB2 0x10604 127 #define C1DRB3 0x10606 128 #define C1DRA01 0x10608 129 #define C1DRA23 0x1060a 130 131 /* p375. 132 */ 133 #define DISPLAY_CNTL 0x70008 134 #define VGA_WRAP_MODE 0x02 135 #define VGA_WRAP_AT_256KB 0x00 136 #define VGA_NO_WRAP 0x02 137 #define GUI_MODE 0x01 138 #define STANDARD_VGA_MODE 0x00 139 #define HIRES_MODE 0x01 140 141 /* p375 142 */ 143 #define PIXPIPE_CONFIG_0 0x70009 144 #define DAC_8_BIT 0x80 145 #define DAC_6_BIT 0x00 146 #define HW_CURSOR_ENABLE 0x10 147 #define EXTENDED_PALETTE 0x01 148 149 /* p375 150 */ 151 #define PIXPIPE_CONFIG_1 0x7000a 152 #define DISPLAY_COLOR_MODE 0x0F 153 #define DISPLAY_VGA_MODE 0x00 154 #define DISPLAY_8BPP_MODE 0x02 155 #define DISPLAY_15BPP_MODE 0x04 156 #define DISPLAY_16BPP_MODE 0x05 157 #define DISPLAY_24BPP_MODE 0x06 158 #define DISPLAY_32BPP_MODE 0x07 159 160 /* p375 161 */ 162 #define PIXPIPE_CONFIG_2 0x7000b 163 #define DISPLAY_GAMMA_ENABLE 0x08 164 #define DISPLAY_GAMMA_DISABLE 0x00 165 #define OVERLAY_GAMMA_ENABLE 0x04 166 #define OVERLAY_GAMMA_DISABLE 0x00 167 168 169 /* p380 170 */ 171 #define DISPLAY_BASE 0x70020 172 #define DISPLAY_BASE_MASK 0x03fffffc 173 174 175 /* Cursor control registers, pp383-384 176 */ 177 /* Desktop (845G, 865G) */ 178 #define CURSOR_CONTROL 0x70080 179 #define CURSOR_ENABLE 0x80000000 180 #define CURSOR_GAMMA_ENABLE 0x40000000 181 #define CURSOR_STRIDE_MASK 0x30000000 182 #define CURSOR_FORMAT_SHIFT 24 183 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 184 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 185 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 186 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 187 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 188 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 189 190 /* Mobile and i810 */ 191 #define CURSOR_A_CONTROL CURSOR_CONTROL 192 #define CURSOR_ORIGIN_SCREEN 0x00 /* i810 only */ 193 #define CURSOR_ORIGIN_DISPLAY 0x1 /* i810 only */ 194 #define CURSOR_MODE 0x27 195 #define CURSOR_MODE_DISABLE 0x00 196 #define CURSOR_MODE_32_4C_AX 0x01 /* i810 only */ 197 #define CURSOR_MODE_64_3C 0x04 198 #define CURSOR_MODE_64_4C_AX 0x05 199 #define CURSOR_MODE_64_4C 0x06 200 #define CURSOR_MODE_64_32B_AX 0x07 201 #define CURSOR_MODE_64_ARGB_AX (0x20 | CURSOR_MODE_64_32B_AX) 202 #define MCURSOR_PIPE_SELECT (1 << 28) 203 #define MCURSOR_PIPE_A 0x00 204 #define MCURSOR_PIPE_B (1 << 28) 205 #define MCURSOR_GAMMA_ENABLE (1 << 26) 206 #define MCURSOR_MEM_TYPE_LOCAL (1 << 25) 207 208 209 #define CURSOR_BASEADDR 0x70084 210 #define CURSOR_A_BASE CURSOR_BASEADDR 211 #define CURSOR_BASEADDR_MASK 0x1FFFFF00 212 #define CURSOR_A_POSITION 0x70088 213 #define CURSOR_POS_SIGN 0x8000 214 #define CURSOR_POS_MASK 0x007FF 215 #define CURSOR_X_SHIFT 0 216 #define CURSOR_Y_SHIFT 16 217 #define CURSOR_X_LO 0x70088 218 #define CURSOR_X_HI 0x70089 219 #define CURSOR_X_POS 0x00 220 #define CURSOR_X_NEG 0x80 221 #define CURSOR_Y_LO 0x7008A 222 #define CURSOR_Y_HI 0x7008B 223 #define CURSOR_Y_POS 0x00 224 #define CURSOR_Y_NEG 0x80 225 226 #define CURSOR_A_PALETTE0 0x70090 227 #define CURSOR_A_PALETTE1 0x70094 228 #define CURSOR_A_PALETTE2 0x70098 229 #define CURSOR_A_PALETTE3 0x7009C 230 231 #define CURSOR_SIZE 0x700A0 232 #define CURSOR_SIZE_MASK 0x3FF 233 #define CURSOR_SIZE_HSHIFT 0 234 #define CURSOR_SIZE_VSHIFT 12 235 236 #define CURSOR_B_CONTROL 0x700C0 237 #define CURSOR_B_BASE 0x700C4 238 #define CURSOR_B_POSITION 0x700C8 239 #define CURSOR_B_PALETTE0 0x700D0 240 #define CURSOR_B_PALETTE1 0x700D4 241 #define CURSOR_B_PALETTE2 0x700D8 242 #define CURSOR_B_PALETTE3 0x700DC 243 244 245 /* Similar registers exist in Device 0 on the i810 (pp55-65), but I'm 246 * not sure they refer to local (graphics) memory. 247 * 248 * These details are for the local memory control registers, 249 * (pp301-310). The test machines are not equiped with local memory, 250 * so nothing is tested. Only a single row seems to be supported. 251 */ 252 #define DRAM_ROW_TYPE 0x3000 253 #define DRAM_ROW_0 0x01 254 #define DRAM_ROW_0_SDRAM 0x01 255 #define DRAM_ROW_0_EMPTY 0x00 256 #define DRAM_ROW_CNTL_LO 0x3001 257 #define DRAM_PAGE_MODE_CTRL 0x10 258 #define DRAM_RAS_TO_CAS_OVRIDE 0x08 259 #define DRAM_CAS_LATENCY 0x04 260 #define DRAM_RAS_TIMING 0x02 261 #define DRAM_RAS_PRECHARGE 0x01 262 #define DRAM_ROW_CNTL_HI 0x3002 263 #define DRAM_REFRESH_RATE 0x18 264 #define DRAM_REFRESH_DISABLE 0x00 265 #define DRAM_REFRESH_60HZ 0x08 266 #define DRAM_REFRESH_FAST_TEST 0x10 267 #define DRAM_REFRESH_RESERVED 0x18 268 #define DRAM_SMS 0x07 269 #define DRAM_SMS_NORMAL 0x00 270 #define DRAM_SMS_NOP_ENABLE 0x01 271 #define DRAM_SMS_ABPCE 0x02 272 #define DRAM_SMS_MRCE 0x03 273 #define DRAM_SMS_CBRCE 0x04 274 275 /* p307 276 */ 277 #define DPMS_SYNC_SELECT 0x5002 278 #define VSYNC_CNTL 0x08 279 #define VSYNC_ON 0x00 280 #define VSYNC_OFF 0x08 281 #define HSYNC_CNTL 0x02 282 #define HSYNC_ON 0x00 283 #define HSYNC_OFF 0x02 284 285 #define GPIOA 0x5010 286 #define GPIOB 0x5014 287 #define GPIOC 0x5018 288 #define GPIOD 0x501c 289 #define GPIOE 0x5020 290 #define GPIOF 0x5024 291 #define GPIOG 0x5028 292 #define GPIOH 0x502c 293 # define GPIO_CLOCK_DIR_MASK (1 << 0) 294 # define GPIO_CLOCK_DIR_IN (0 << 1) 295 # define GPIO_CLOCK_DIR_OUT (1 << 1) 296 # define GPIO_CLOCK_VAL_MASK (1 << 2) 297 # define GPIO_CLOCK_VAL_OUT (1 << 3) 298 # define GPIO_CLOCK_VAL_IN (1 << 4) 299 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 300 # define GPIO_DATA_DIR_MASK (1 << 8) 301 # define GPIO_DATA_DIR_IN (0 << 9) 302 # define GPIO_DATA_DIR_OUT (1 << 9) 303 # define GPIO_DATA_VAL_MASK (1 << 10) 304 # define GPIO_DATA_VAL_OUT (1 << 11) 305 # define GPIO_DATA_VAL_IN (1 << 12) 306 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 307 308 /* GMBus registers for hardware-assisted (non-bitbanging) I2C access */ 309 #define GMBUS0 0x5100 310 #define GMBUS1 0x5104 311 #define GMBUS2 0x5108 312 #define GMBUS3 0x510c 313 #define GMBUS4 0x5110 314 #define GMBUS5 0x5120 315 316 /* p317, 319 317 */ 318 #define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */ 319 #define VCLK2_VCO_N 0x600a 320 #define VCLK2_VCO_DIV_SEL 0x6012 321 322 #define VCLK_DIVISOR_VGA0 0x6000 323 #define VCLK_DIVISOR_VGA1 0x6004 324 #define VCLK_POST_DIV 0x6010 325 /* Selects a post divisor of 4 instead of 2. */ 326 # define VGA1_PD_P2_DIV_4 (1 << 15) 327 /* Overrides the p2 post divisor field */ 328 # define VGA1_PD_P1_DIV_2 (1 << 13) 329 # define VGA1_PD_P1_SHIFT 8 330 /* P1 value is 2 greater than this field */ 331 # define VGA1_PD_P1_MASK (0x1f << 8) 332 /* Selects a post divisor of 4 instead of 2. */ 333 # define VGA0_PD_P2_DIV_4 (1 << 7) 334 /* Overrides the p2 post divisor field */ 335 # define VGA0_PD_P1_DIV_2 (1 << 5) 336 # define VGA0_PD_P1_SHIFT 0 337 /* P1 value is 2 greater than this field */ 338 # define VGA0_PD_P1_MASK (0x1f << 0) 339 340 #define POST_DIV_SELECT 0x70 341 #define POST_DIV_1 0x00 342 #define POST_DIV_2 0x10 343 #define POST_DIV_4 0x20 344 #define POST_DIV_8 0x30 345 #define POST_DIV_16 0x40 346 #define POST_DIV_32 0x50 347 #define VCO_LOOP_DIV_BY_4M 0x00 348 #define VCO_LOOP_DIV_BY_16M 0x04 349 350 351 /* Instruction Parser Mode Register 352 * - p281 353 * - 2 new bits. 354 */ 355 #define INST_PM 0x20c0 356 #define AGP_SYNC_PACKET_FLUSH_ENABLE 0x20 /* reserved */ 357 #define SYNC_PACKET_FLUSH_ENABLE 0x10 358 #define TWO_D_INST_DISABLE 0x08 359 #define THREE_D_INST_DISABLE 0x04 360 #define STATE_VAR_UPDATE_DISABLE 0x02 361 #define PAL_STIP_DISABLE 0x01 362 #define GEN6_GLOBAL_DEBUG_ENABLE 0x10 363 364 365 #define MEMMODE 0x20dc 366 367 368 /* Instruction parser error register. p279 369 */ 370 #define IPEIR 0x2088 371 #define IPEHR 0x208C 372 373 #define INSTDONE 0x2090 374 #define NOP_ID 0x2094 375 376 #define SCPD0 0x209c /* debug */ 377 #define INST_PS 0x20c4 378 #define IPEIR_I965 0x2064 /* i965 */ 379 #define IPEHR_I965 0x2068 /* i965 */ 380 #define INSTDONE_I965 0x206c 381 #define GEN6_INSTDONE_1 0x206c 382 #define INST_PS_I965 0x2070 383 384 /* Current active ring head address: 385 */ 386 #define ACTHD_I965 0x2074 387 #define ACTHD 0x20C8 388 389 /* Current primary/secondary DMA fetch addresses: 390 */ 391 #define DMA_FADD_P 0x2078 392 #define DMA_FADD_S 0x20d4 393 #define INSTDONE_1 0x207c 394 #define GEN6_INSTDONE_2 0x207c 395 396 #define CACHE_MODE_0 0x2120 397 #define CACHE_MODE_1 0x2124 398 #define MI_MODE 0x209c 399 #define MI_DISPLAY_POWER_DOWN 0x20e0 400 #define MI_ARB_STATE 0x20e4 401 #define MI_RDRET_STATE 0x20fc 402 403 /* Start addresses for each of the primary rings: 404 */ 405 #define PR0_STR 0x20f0 406 #define PR1_STR 0x20f4 407 #define PR2_STR 0x20f8 408 409 #define WIZ_CTL 0x7c00 410 #define WIZ_CTL_SINGLE_SUBSPAN (1<<6) 411 #define WIZ_CTL_IGNORE_STALLS (1<<5) 412 413 #define SVG_WORK_CTL 0x7408 414 415 #define TS_CTL 0x7e00 416 #define TS_MUX_ERR_CODE (0<<8) 417 #define TS_MUX_URB_0 (1<<8) 418 #define TS_MUX_DISPATCH_ID_0 (10<<8) 419 #define TS_MUX_ERR_CODE_VALID (15<<8) 420 #define TS_MUX_TID_0 (16<<8) 421 #define TS_MUX_EUID_0 (18<<8) 422 #define TS_MUX_FFID_0 (22<<8) 423 #define TS_MUX_EOT (26<<8) 424 #define TS_MUX_SIDEBAND_0 (27<<8) 425 #define TS_SNAP_ALL_CHILD (1<<2) 426 #define TS_SNAP_ALL_ROOT (1<<1) 427 #define TS_SNAP_ENABLE (1<<0) 428 429 #define TS_DEBUG_DATA 0x7e0c 430 431 #define TD_CTL 0x8000 432 #define TD_CTL2 0x8004 433 434 435 #define ECOSKPD 0x21d0 436 #define EXCC 0x2028 437 438 /* I965 debug regs: 439 */ 440 #define IA_VERTICES_COUNT_QW 0x2310 441 #define IA_PRIMITIVES_COUNT_QW 0x2318 442 #define VS_INVOCATION_COUNT_QW 0x2320 443 #define GS_INVOCATION_COUNT_QW 0x2328 444 #define GS_PRIMITIVES_COUNT_QW 0x2330 445 #define CL_INVOCATION_COUNT_QW 0x2338 446 #define CL_PRIMITIVES_COUNT_QW 0x2340 447 #define PS_INVOCATION_COUNT_QW 0x2348 448 #define PS_DEPTH_COUNT_QW 0x2350 449 #define TIMESTAMP_QW 0x2358 450 #define CLKCMP_QW 0x2360 451 452 453 454 455 456 457 /* General error reporting regs, p296 458 */ 459 #define EIR 0x20B0 460 #define EMR 0x20B4 461 #define ESR 0x20B8 462 # define ERR_VERTEX_MAX (1 << 5) /* lpt/cst */ 463 # define ERR_PGTBL_ERROR (1 << 4) 464 # define ERR_DISPLAY_OVERLAY_UNDERRUN (1 << 3) 465 # define ERR_MAIN_MEMORY_REFRESH (1 << 1) 466 # define ERR_INSTRUCTION_ERROR (1 << 0) 467 468 469 /* Interrupt Control Registers 470 * - new bits for i810 471 * - new register hwstam (mask) 472 */ 473 #define HWS_PGA 0x2080 474 #define PWRCTXA 0x2088 /* 965GM+ only */ 475 #define PWRCTX_EN (1<<0) 476 #define HWSTAM 0x2098 /* p290 */ 477 #define IER 0x20a0 /* p291 */ 478 #define IIR 0x20a4 /* p292 */ 479 #define IMR 0x20a8 /* p293 */ 480 #define ISR 0x20ac /* p294 */ 481 #define HW_ERROR 0x8000 482 #define SYNC_STATUS_TOGGLE 0x1000 483 #define DPY_0_FLIP_PENDING 0x0800 484 #define DPY_1_FLIP_PENDING 0x0400 /* not implemented on i810 */ 485 #define OVL_0_FLIP_PENDING 0x0200 486 #define OVL_1_FLIP_PENDING 0x0100 /* not implemented on i810 */ 487 #define DPY_0_VBLANK 0x0080 488 #define DPY_0_EVENT 0x0040 489 #define DPY_1_VBLANK 0x0020 /* not implemented on i810 */ 490 #define DPY_1_EVENT 0x0010 /* not implemented on i810 */ 491 #define HOST_PORT_EVENT 0x0008 /* */ 492 #define CAPTURE_EVENT 0x0004 /* */ 493 #define USER_DEFINED 0x0002 494 #define BREAKPOINT 0x0001 495 496 497 #define INTR_RESERVED (0x6000 | \ 498 DPY_1_FLIP_PENDING | \ 499 OVL_1_FLIP_PENDING | \ 500 DPY_1_VBLANK | \ 501 DPY_1_EVENT | \ 502 HOST_PORT_EVENT | \ 503 CAPTURE_EVENT ) 504 505 /* FIFO Watermark and Burst Length Control Register 506 * 507 * - different offset and contents on i810 (p299) (fewer bits per field) 508 * - some overlay fields added 509 * - what does it all mean? 510 */ 511 #define FWATER_BLC 0x20d8 512 #define FWATER_BLC2 0x20dc 513 #define MM_BURST_LENGTH 0x00700000 514 #define MM_FIFO_WATERMARK 0x0001F000 515 #define LM_BURST_LENGTH 0x00000700 516 #define LM_FIFO_WATERMARK 0x0000001F 517 518 519 /* Fence/Tiling ranges [0..7] 520 */ 521 #define FENCE 0x2000 522 #define FENCE_NR 8 523 524 #define FENCE_NEW 0x3000 525 #define FENCE_NEW_NR 16 526 527 #define FENCE_LINEAR 0 528 #define FENCE_XMAJOR 1 529 #define FENCE_YMAJOR 2 530 531 #define I915G_FENCE_START_MASK 0x0ff00000 532 533 #define I830_FENCE_START_MASK 0x07f80000 534 535 #define FENCE_START_MASK 0x03F80000 536 #define FENCE_X_MAJOR 0x00000000 537 #define FENCE_Y_MAJOR 0x00001000 538 #define FENCE_SIZE_MASK 0x00000700 539 #define FENCE_SIZE_512K 0x00000000 540 #define FENCE_SIZE_1M 0x00000100 541 #define FENCE_SIZE_2M 0x00000200 542 #define FENCE_SIZE_4M 0x00000300 543 #define FENCE_SIZE_8M 0x00000400 544 #define FENCE_SIZE_16M 0x00000500 545 #define FENCE_SIZE_32M 0x00000600 546 #define FENCE_SIZE_64M 0x00000700 547 #define I915G_FENCE_SIZE_1M 0x00000000 548 #define I915G_FENCE_SIZE_2M 0x00000100 549 #define I915G_FENCE_SIZE_4M 0x00000200 550 #define I915G_FENCE_SIZE_8M 0x00000300 551 #define I915G_FENCE_SIZE_16M 0x00000400 552 #define I915G_FENCE_SIZE_32M 0x00000500 553 #define I915G_FENCE_SIZE_64M 0x00000600 554 #define I915G_FENCE_SIZE_128M 0x00000700 555 #define I965_FENCE_X_MAJOR 0x00000000 556 #define I965_FENCE_Y_MAJOR 0x00000002 557 #define FENCE_PITCH_1 0x00000000 558 #define FENCE_PITCH_2 0x00000010 559 #define FENCE_PITCH_4 0x00000020 560 #define FENCE_PITCH_8 0x00000030 561 #define FENCE_PITCH_16 0x00000040 562 #define FENCE_PITCH_32 0x00000050 563 #define FENCE_PITCH_64 0x00000060 564 #define FENCE_VALID 0x00000001 565 566 #define FENCE_REG_SANDYBRIDGE_0 0x100000 567 568 /* Registers to control page table, p274 569 */ 570 #define PGETBL_CTL 0x2020 571 #define PGETBL_ADDR_MASK 0xFFFFF000 572 #define PGETBL_ENABLE_MASK 0x00000001 573 #define PGETBL_ENABLED 0x00000001 574 /* Added in 965G, this field has the actual size of the global GTT */ 575 #define PGETBL_SIZE_MASK 0x0000000e 576 #define PGETBL_SIZE_512KB (0 << 1) 577 #define PGETBL_SIZE_256KB (1 << 1) 578 #define PGETBL_SIZE_128KB (2 << 1) 579 #define PGETBL_SIZE_1MB (3 << 1) 580 #define PGETBL_SIZE_2MB (4 << 1) 581 #define PGETBL_SIZE_1_5MB (5 << 1) 582 #define G33_PGETBL_SIZE_MASK (3 << 8) 583 #define G33_PGETBL_SIZE_1M (1 << 8) 584 #define G33_PGETBL_SIZE_2M (2 << 8) 585 586 #define I830_PTE_BASE 0x10000 587 #define PTE_ADDRESS_MASK 0xfffff000 588 #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */ 589 #define PTE_MAPPING_TYPE_UNCACHED (0 << 1) 590 #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */ 591 #define PTE_MAPPING_TYPE_CACHED (3 << 1) 592 #define PTE_MAPPING_TYPE_MASK (3 << 1) 593 #define PTE_VALID (1 << 0) 594 595 /* @defgroup PGE_ERR 596 * @{ 597 */ 598 /* Page table debug register for i845 */ 599 #define PGE_ERR 0x2024 600 #define PGE_ERR_ADDR_MASK 0xFFFFF000 601 #define PGE_ERR_ID_MASK 0x00000038 602 #define PGE_ERR_CAPTURE 0x00000000 603 #define PGE_ERR_OVERLAY 0x00000008 604 #define PGE_ERR_DISPLAY 0x00000010 605 #define PGE_ERR_HOST 0x00000018 606 #define PGE_ERR_RENDER 0x00000020 607 #define PGE_ERR_BLITTER 0x00000028 608 #define PGE_ERR_MAPPING 0x00000030 609 #define PGE_ERR_CMD_PARSER 0x00000038 610 #define PGE_ERR_TYPE_MASK 0x00000007 611 #define PGE_ERR_INV_TABLE 0x00000000 612 #define PGE_ERR_INV_PTE 0x00000001 613 #define PGE_ERR_MIXED_TYPES 0x00000002 614 #define PGE_ERR_PAGE_MISS 0x00000003 615 #define PGE_ERR_ILLEGAL_TRX 0x00000004 616 #define PGE_ERR_LOCAL_MEM 0x00000005 617 #define PGE_ERR_TILED 0x00000006 618 /* @} */ 619 620 /* @defgroup PGTBL_ER 621 * @{ 622 */ 623 /* Page table debug register for i945 */ 624 # define PGTBL_ER 0x2024 625 # define PGTBL_ERR_MT_TILING (1 << 27) 626 # define PGTBL_ERR_MT_GTT_PTE (1 << 26) 627 # define PGTBL_ERR_LC_TILING (1 << 25) 628 # define PGTBL_ERR_LC_GTT_PTE (1 << 24) 629 # define PGTBL_ERR_BIN_VERTEXDATA_GTT_PTE (1 << 23) 630 # define PGTBL_ERR_BIN_INSTRUCTION_GTT_PTE (1 << 22) 631 # define PGTBL_ERR_CS_VERTEXDATA_GTT_PTE (1 << 21) 632 # define PGTBL_ERR_CS_INSTRUCTION_GTT_PTE (1 << 20) 633 # define PGTBL_ERR_CS_GTT (1 << 19) 634 # define PGTBL_ERR_OVERLAY_TILING (1 << 18) 635 # define PGTBL_ERR_OVERLAY_GTT_PTE (1 << 16) 636 # define PGTBL_ERR_DISPC_TILING (1 << 14) 637 # define PGTBL_ERR_DISPC_GTT_PTE (1 << 12) 638 # define PGTBL_ERR_DISPB_TILING (1 << 10) 639 # define PGTBL_ERR_DISPB_GTT_PTE (1 << 8) 640 # define PGTBL_ERR_DISPA_TILING (1 << 6) 641 # define PGTBL_ERR_DISPA_GTT_PTE (1 << 4) 642 # define PGTBL_ERR_HOST_PTE_DATA (1 << 1) 643 # define PGTBL_ERR_HOST_GTT_PTE (1 << 0) 644 /* @} */ 645 646 /* Ring buffer registers, p277, overview p19 647 */ 648 #define LP_RING 0x2030 649 #define HP_RING 0x2040 650 651 #define RING_TAIL 0x00 652 #define TAIL_ADDR 0x000FFFF8 653 #define I830_TAIL_MASK 0x001FFFF8 654 655 #define RING_HEAD 0x04 656 #define HEAD_WRAP_COUNT 0xFFE00000 657 #define HEAD_WRAP_ONE 0x00200000 658 #define HEAD_ADDR 0x001FFFFC 659 #define I830_HEAD_MASK 0x001FFFFC 660 661 #define RING_START 0x08 662 #define START_ADDR 0x03FFFFF8 663 #define I830_RING_START_MASK 0xFFFFF000 664 665 #define RING_LEN 0x0C 666 #define RING_NR_PAGES 0x001FF000 667 #define I830_RING_NR_PAGES 0x001FF000 668 #define RING_REPORT_MASK 0x00000006 669 #define RING_REPORT_64K 0x00000002 670 #define RING_REPORT_128K 0x00000004 671 #define RING_NO_REPORT 0x00000000 672 #define RING_VALID_MASK 0x00000001 673 #define RING_VALID 0x00000001 674 #define RING_INVALID 0x00000000 675 676 677 678 /* BitBlt Instructions 679 * 680 * There are many more masks & ranges yet to add. 681 */ 682 #define BR00_BITBLT_CLIENT 0x40000000 683 #define BR00_OP_COLOR_BLT 0x10000000 684 #define BR00_OP_SRC_COPY_BLT 0x10C00000 685 #define BR00_OP_FULL_BLT 0x11400000 686 #define BR00_OP_MONO_SRC_BLT 0x11800000 687 #define BR00_OP_MONO_SRC_COPY_BLT 0x11000000 688 #define BR00_OP_MONO_PAT_BLT 0x11C00000 689 #define BR00_OP_MONO_SRC_COPY_IMMEDIATE_BLT (0x61 << 22) 690 #define BR00_OP_TEXT_IMMEDIATE_BLT 0xc000000 691 692 693 #define BR00_TPCY_DISABLE 0x00000000 694 #define BR00_TPCY_ENABLE 0x00000010 695 696 #define BR00_TPCY_ROP 0x00000000 697 #define BR00_TPCY_NO_ROP 0x00000020 698 #define BR00_TPCY_EQ 0x00000000 699 #define BR00_TPCY_NOT_EQ 0x00000040 700 701 #define BR00_PAT_MSB_FIRST 0x00000000 /* ? */ 702 703 #define BR00_PAT_VERT_ALIGN 0x000000e0 704 705 #define BR00_LENGTH 0x0000000F 706 707 #define BR09_DEST_ADDR 0x03FFFFFF 708 709 #define BR11_SOURCE_PITCH 0x00003FFF 710 711 #define BR12_SOURCE_ADDR 0x03FFFFFF 712 713 #define BR13_SOLID_PATTERN 0x80000000 714 #define BR13_RIGHT_TO_LEFT 0x40000000 715 #define BR13_LEFT_TO_RIGHT 0x00000000 716 #define BR13_MONO_TRANSPCY 0x20000000 717 #define BR13_MONO_PATN_TRANS 0x10000000 718 #define BR13_USE_DYN_DEPTH 0x04000000 719 #define BR13_DYN_8BPP 0x00000000 720 #define BR13_DYN_16BPP 0x01000000 721 #define BR13_DYN_24BPP 0x02000000 722 #define BR13_ROP_MASK 0x00FF0000 723 #define BR13_DEST_PITCH 0x0000FFFF 724 #define BR13_PITCH_SIGN_BIT 0x00008000 725 726 #define BR14_DEST_HEIGHT 0xFFFF0000 727 #define BR14_DEST_WIDTH 0x0000FFFF 728 729 #define BR15_PATTERN_ADDR 0x03FFFFFF 730 731 #define BR16_SOLID_PAT_COLOR 0x00FFFFFF 732 #define BR16_BACKGND_PAT_CLR 0x00FFFFFF 733 734 #define BR17_FGND_PAT_CLR 0x00FFFFFF 735 736 #define BR18_SRC_BGND_CLR 0x00FFFFFF 737 #define BR19_SRC_FGND_CLR 0x00FFFFFF 738 739 740 /* Instruction parser instructions 741 */ 742 743 #define INST_PARSER_CLIENT 0x00000000 744 #define INST_OP_FLUSH 0x02000000 745 #define INST_FLUSH_MAP_CACHE 0x00000001 746 747 748 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) 749 750 751 /* Registers in the i810 host-pci bridge pci config space which affect 752 * the i810 graphics operations. 753 */ 754 #define SMRAM_MISCC 0x70 755 #define GMS 0x000000c0 756 #define GMS_DISABLE 0x00000000 757 #define GMS_ENABLE_BARE 0x00000040 758 #define GMS_ENABLE_512K 0x00000080 759 #define GMS_ENABLE_1M 0x000000c0 760 #define USMM 0x00000030 761 #define USMM_DISABLE 0x00000000 762 #define USMM_TSEG_ZERO 0x00000010 763 #define USMM_TSEG_512K 0x00000020 764 #define USMM_TSEG_1M 0x00000030 765 #define GFX_MEM_WIN_SIZE 0x00010000 766 #define GFX_MEM_WIN_32M 0x00010000 767 #define GFX_MEM_WIN_64M 0x00000000 768 769 /* Overkill? I don't know. Need to figure out top of mem to make the 770 * SMRAM calculations come out. Linux seems to have problems 771 * detecting it all on its own, so this seems a reasonable double 772 * check to any user supplied 'mem=...' boot param. 773 * 774 * ... unfortunately this reg doesn't work according to spec on the 775 * test hardware. 776 */ 777 #define WHTCFG_PAMR_DRP 0x50 778 #define SYS_DRAM_ROW_0_SHIFT 16 779 #define SYS_DRAM_ROW_1_SHIFT 20 780 #define DRAM_MASK 0x0f 781 #define DRAM_VALUE_0 0 782 #define DRAM_VALUE_1 8 783 /* No 2 value defined */ 784 #define DRAM_VALUE_3 16 785 #define DRAM_VALUE_4 16 786 #define DRAM_VALUE_5 24 787 #define DRAM_VALUE_6 32 788 #define DRAM_VALUE_7 32 789 #define DRAM_VALUE_8 48 790 #define DRAM_VALUE_9 64 791 #define DRAM_VALUE_A 64 792 #define DRAM_VALUE_B 96 793 #define DRAM_VALUE_C 128 794 #define DRAM_VALUE_D 128 795 #define DRAM_VALUE_E 192 796 #define DRAM_VALUE_F 256 /* nice one, geezer */ 797 #define LM_FREQ_MASK 0x10 798 #define LM_FREQ_133 0x10 799 #define LM_FREQ_100 0x00 800 801 802 803 804 /* These are 3d state registers, but the state is invarient, so we let 805 * the X server handle it: 806 */ 807 808 809 810 /* GFXRENDERSTATE_COLOR_CHROMA_KEY, p135 811 */ 812 #define GFX_OP_COLOR_CHROMA_KEY ((0x3<<29)|(0x1d<<24)|(0x2<<16)|0x1) 813 #define CC1_UPDATE_KILL_WRITE (1<<28) 814 #define CC1_ENABLE_KILL_WRITE (1<<27) 815 #define CC1_DISABLE_KILL_WRITE 0 816 #define CC1_UPDATE_COLOR_IDX (1<<26) 817 #define CC1_UPDATE_CHROMA_LOW (1<<25) 818 #define CC1_UPDATE_CHROMA_HI (1<<24) 819 #define CC1_CHROMA_LOW_MASK ((1<<24)-1) 820 #define CC2_COLOR_IDX_SHIFT 24 821 #define CC2_COLOR_IDX_MASK (0xff<<24) 822 #define CC2_CHROMA_HI_MASK ((1<<24)-1) 823 824 825 #define GFX_CMD_CONTEXT_SEL ((0<<29)|(0x5<<23)) 826 #define CS_UPDATE_LOAD (1<<17) 827 #define CS_UPDATE_USE (1<<16) 828 #define CS_UPDATE_LOAD (1<<17) 829 #define CS_LOAD_CTX0 0 830 #define CS_LOAD_CTX1 (1<<8) 831 #define CS_USE_CTX0 0 832 #define CS_USE_CTX1 (1<<0) 833 834 /* I810 LCD/TV registers */ 835 #define LCD_TV_HTOTAL 0x60000 836 #define LCD_TV_C 0x60018 837 #define LCD_TV_OVRACT 0x6001C 838 839 #define LCD_TV_ENABLE (1 << 31) 840 #define LCD_TV_VGAMOD (1 << 28) 841 842 /* I830 CRTC registers */ 843 #define HTOTAL_A 0x60000 844 #define HBLANK_A 0x60004 845 #define HSYNC_A 0x60008 846 #define VTOTAL_A 0x6000c 847 #define VBLANK_A 0x60010 848 #define VSYNC_A 0x60014 849 #define PIPEASRC 0x6001c 850 #define BCLRPAT_A 0x60020 851 #define VSYNCSHIFT_A 0x60028 852 853 #define HTOTAL_B 0x61000 854 #define HBLANK_B 0x61004 855 #define HSYNC_B 0x61008 856 #define VTOTAL_B 0x6100c 857 #define VBLANK_B 0x61010 858 #define VSYNC_B 0x61014 859 #define PIPEBSRC 0x6101c 860 #define BCLRPAT_B 0x61020 861 #define VSYNCSHIFT_B 0x61028 862 863 #define HTOTAL_C 0x62000 864 #define HBLANK_C 0x62004 865 #define HSYNC_C 0x62008 866 #define VTOTAL_C 0x6200c 867 #define VBLANK_C 0x62010 868 #define VSYNC_C 0x62014 869 #define PIPECSRC 0x6201c 870 #define BCLRPAT_C 0x62020 871 #define VSYNCSHIFT_C 0x62028 872 873 #define HTOTAL_EDP 0x6F000 874 #define HBLANK_EDP 0x6F004 875 #define HSYNC_EDP 0x6F008 876 #define VTOTAL_EDP 0x6F00c 877 #define VBLANK_EDP 0x6F010 878 #define VSYNC_EDP 0x6F014 879 #define VSYNCSHIFT_EDP 0x6F028 880 881 #define PP_STATUS 0x61200 882 # define PP_ON (1 << 31) 883 /* 884 * Indicates that all dependencies of the panel are on: 885 * 886 * - PLL enabled 887 * - pipe enabled 888 * - LVDS/DVOB/DVOC on 889 */ 890 # define PP_READY (1 << 30) 891 # define PP_SEQUENCE_NONE (0 << 28) 892 # define PP_SEQUENCE_ON (1 << 28) 893 # define PP_SEQUENCE_OFF (2 << 28) 894 # define PP_SEQUENCE_MASK 0x30000000 895 896 #define PP_CONTROL 0x61204 897 # define POWER_DOWN_ON_RESET (1 << 1) 898 # define POWER_TARGET_ON (1 << 0) 899 900 #define PP_ON_DELAYS 0x61208 901 #define PP_OFF_DELAYS 0x6120c 902 #define PP_DIVISOR 0x61210 903 904 #define PFIT_CONTROL 0x61230 905 # define PFIT_ENABLE (1 << 31) 906 /* Pre-965 */ 907 # define VERT_INTERP_DISABLE (0 << 10) 908 # define VERT_INTERP_BILINEAR (1 << 10) 909 # define VERT_INTERP_MASK (3 << 10) 910 # define VERT_AUTO_SCALE (1 << 9) 911 # define HORIZ_INTERP_DISABLE (0 << 6) 912 # define HORIZ_INTERP_BILINEAR (1 << 6) 913 # define HORIZ_INTERP_MASK (3 << 6) 914 # define HORIZ_AUTO_SCALE (1 << 5) 915 # define PANEL_8TO6_DITHER_ENABLE (1 << 3) 916 /* 965+ */ 917 # define PFIT_PIPE_MASK (3 << 29) 918 # define PFIT_PIPE_SHIFT 29 919 # define PFIT_SCALING_MODE_MASK (7 << 26) 920 # define PFIT_SCALING_AUTO (0 << 26) 921 # define PFIT_SCALING_PROGRAMMED (1 << 26) 922 # define PFIT_SCALING_PILLAR (2 << 26) 923 # define PFIT_SCALING_LETTER (3 << 26) 924 # define PFIT_FILTER_SELECT_MASK (3 << 24) 925 # define PFIT_FILTER_FUZZY (0 << 24) 926 # define PFIT_FILTER_CRISP (1 << 24) 927 # define PFIT_FILTER_MEDIAN (2 << 24) 928 929 #define PFIT_PGM_RATIOS 0x61234 930 /* Pre-965 */ 931 # define PFIT_VERT_SCALE_SHIFT 20 932 # define PFIT_VERT_SCALE_MASK 0xfff00000 933 # define PFIT_HORIZ_SCALE_SHIFT 4 934 # define PFIT_HORIZ_SCALE_MASK 0x0000fff0 935 /* 965+ */ 936 # define PFIT_VERT_SCALE_SHIFT_965 16 937 # define PFIT_VERT_SCALE_MASK_965 0x1fff0000 938 # define PFIT_HORIZ_SCALE_SHIFT_965 0 939 # define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 940 941 #define DPLL_A 0x06014 942 #define DPLL_B 0x06018 943 # define DPLL_VCO_ENABLE (1 << 31) 944 # define DPLL_DVO_HIGH_SPEED (1 << 30) 945 # define DPLL_SYNCLOCK_ENABLE (1 << 29) 946 # define DPLL_VGA_MODE_DIS (1 << 28) 947 # define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 948 # define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 949 # define DPLL_MODE_MASK (3 << 26) 950 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 951 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 952 # define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 953 # define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 954 # define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 955 # define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 956 # define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */ 957 /* 958 * The i830 generation, in DAC/serial mode, defines p1 as two plus this 959 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. 960 */ 961 # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 962 /* 963 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 964 * this field (only one bit may be set). 965 */ 966 # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 967 # define DPLL_FPA01_P1_POST_DIV_SHIFT 16 968 # define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15 969 # define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */ 970 # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 971 # define PLL_REF_INPUT_DREFCLK (0 << 13) 972 # define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 973 # define PLL_REF_INPUT_SUPER_SSC (1 << 13) /* Ironlake: 120M SSC */ 974 # define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 975 # define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 976 # define PLL_REF_INPUT_MASK (3 << 13) 977 # define PLL_REF_INPUT_DMICLK (5 << 13) /* Ironlake: DMI refclk */ 978 # define PLL_LOAD_PULSE_PHASE_SHIFT 9 979 /* 980 * Parallel to Serial Load Pulse phase selection. 981 * Selects the phase for the 10X DPLL clock for the PCIe 982 * digital display port. The range is 4 to 13; 10 or more 983 * is just a flip delay. The default is 6 984 */ 985 # define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 986 # define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 987 /* Ironlake */ 988 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 989 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 990 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1)<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) 991 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 992 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 993 994 /* 995 * SDVO multiplier for 945G/GM. Not used on 965. 996 * 997 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 998 */ 999 # define SDVO_MULTIPLIER_MASK 0x000000ff 1000 # define SDVO_MULTIPLIER_SHIFT_HIRES 4 1001 # define SDVO_MULTIPLIER_SHIFT_VGA 0 1002 1003 /* @defgroup DPLL_MD 1004 * @{ 1005 */ 1006 /* Pipe A SDVO/UDI clock multiplier/divider register for G965. */ 1007 #define DPLL_A_MD 0x0601c 1008 /* Pipe B SDVO/UDI clock multiplier/divider register for G965. */ 1009 #define DPLL_B_MD 0x06020 1010 /* 1011 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 1012 * 1013 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 1014 */ 1015 # define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 1016 # define DPLL_MD_UDI_DIVIDER_SHIFT 24 1017 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 1018 # define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 1019 # define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 1020 /* 1021 * SDVO/UDI pixel multiplier. 1022 * 1023 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 1024 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 1025 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 1026 * dummy bytes in the datastream at an increased clock rate, with both sides of 1027 * the link knowing how many bytes are fill. 1028 * 1029 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 1030 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 1031 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 1032 * through an SDVO command. 1033 * 1034 * This register field has values of multiplication factor minus 1, with 1035 * a maximum multiplier of 5 for SDVO. 1036 */ 1037 # define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 1038 # define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 1039 /* SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 1040 * This best be set to the default value (3) or the CRT won't work. No, 1041 * I don't entirely understand what this does... 1042 */ 1043 # define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 1044 # define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 1045 /* @} */ 1046 1047 #define DPLL_TEST 0x606c 1048 # define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 1049 # define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 1050 # define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 1051 # define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 1052 # define DPLLB_TEST_N_BYPASS (1 << 19) 1053 # define DPLLB_TEST_M_BYPASS (1 << 18) 1054 # define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 1055 # define DPLLA_TEST_N_BYPASS (1 << 3) 1056 # define DPLLA_TEST_M_BYPASS (1 << 2) 1057 # define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 1058 1059 #define D_STATE 0x6104 1060 #define DSPCLK_GATE_D 0x6200 1061 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 1062 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 1063 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 1064 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 1065 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 1066 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 1067 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 1068 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 1069 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 1070 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 1071 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 1072 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 1073 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 1074 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 1075 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 1076 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 1077 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 1078 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 1079 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 1080 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 1081 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 1082 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 1083 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 1084 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 1085 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 1086 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 1087 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 1088 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 1089 /* 1090 * This bit must be set on the 830 to prevent hangs when turning off the 1091 * overlay scaler. 1092 */ 1093 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 1094 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 1095 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 1096 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 1097 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 1098 1099 #define RENCLK_GATE_D1 0x6204 1100 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 1101 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 1102 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 1103 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 1104 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 1105 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 1106 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 1107 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 1108 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 1109 /* This bit must be unset on 855,865 */ 1110 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 1111 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 1112 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 1113 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 1114 /* This bit must be set on 855,865. */ 1115 # define SV_CLOCK_GATE_DISABLE (1 << 0) 1116 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 1117 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 1118 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 1119 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 1120 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 1121 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 1122 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 1123 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 1124 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 1125 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 1126 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 1127 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 1128 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 1129 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 1130 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 1131 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 1132 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 1133 1134 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 1135 /* This bit must always be set on 965G/965GM */ 1136 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 1137 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 1138 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 1139 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 1140 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 1141 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 1142 /* This bit must always be set on 965G */ 1143 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 1144 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 1145 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 1146 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 1147 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 1148 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 1149 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 1150 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 1151 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 1152 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 1153 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 1154 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 1155 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 1156 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 1157 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 1158 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 1159 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 1160 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 1161 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 1162 1163 #define RENCLK_GATE_D2 0x6208 1164 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 1165 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 1166 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 1167 #define RAMCLK_GATE_D 0x6210 /* CRL only */ 1168 #define DEUC 0x6214 /* CRL only */ 1169 1170 /* 1171 * This is a PCI config space register to manipulate backlight brightness 1172 * It is used when the BLM_LEGACY_MODE is turned on. When enabled, the first 1173 * byte of this config register sets brightness within the range from 1174 * 0 to 0xff 1175 */ 1176 #define LEGACY_BACKLIGHT_BRIGHTNESS 0xf4 1177 1178 #define BLC_PWM_CTL 0x61254 1179 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 1180 #define BACKLIGHT_MODULATION_FREQ_SHIFT2 (16) 1181 /* 1182 * This is the most significant 15 bits of the number of backlight cycles in a 1183 * complete cycle of the modulated backlight control. 1184 * 1185 * The actual value is this field multiplied by two. 1186 */ 1187 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 1188 #define BACKLIGHT_MODULATION_FREQ_MASK2 (0xffff << 16) 1189 #define BLM_LEGACY_MODE (1 << 16) 1190 1191 /* 1192 * This is the number of cycles out of the backlight modulation cycle for which 1193 * the backlight is on. 1194 * 1195 * This field must be no greater than the number of cycles in the complete 1196 * backlight modulation cycle. 1197 */ 1198 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 1199 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 1200 1201 /* On 965+ backlight control is in another register */ 1202 #define BLC_PWM_CTL2 0x61250 1203 #define BLM_LEGACY_MODE2 (1 << 30) 1204 1205 #define BLM_CTL 0x61260 1206 #define BLM_THRESHOLD_0 0x61270 1207 #define BLM_THRESHOLD_1 0x61274 1208 #define BLM_THRESHOLD_2 0x61278 1209 #define BLM_THRESHOLD_3 0x6127c 1210 #define BLM_THRESHOLD_4 0x61280 1211 #define BLM_THRESHOLD_5 0x61284 1212 1213 #define BLM_ACCUMULATOR_0 0x61290 1214 #define BLM_ACCUMULATOR_1 0x61294 1215 #define BLM_ACCUMULATOR_2 0x61298 1216 #define BLM_ACCUMULATOR_3 0x6129c 1217 #define BLM_ACCUMULATOR_4 0x612a0 1218 #define BLM_ACCUMULATOR_5 0x612a4 1219 1220 #define FPA0 0x06040 1221 #define FPA1 0x06044 1222 #define FPB0 0x06048 1223 #define FPB1 0x0604c 1224 # define FP_N_DIV_MASK 0x003f0000 1225 # define FP_N_IGD_DIV_MASK 0x00ff0000 1226 # define FP_N_DIV_SHIFT 16 1227 # define FP_M1_DIV_MASK 0x00003f00 1228 # define FP_M1_DIV_SHIFT 8 1229 # define FP_M2_DIV_MASK 0x0000003f 1230 # define FP_M2_IGD_DIV_MASK 0x000000ff 1231 # define FP_M2_DIV_SHIFT 0 1232 1233 #define PORT_HOTPLUG_EN 0x61110 1234 # define HDMIB_HOTPLUG_INT_EN (1 << 29) 1235 # define HDMIC_HOTPLUG_INT_EN (1 << 28) 1236 # define HDMID_HOTPLUG_INT_EN (1 << 27) 1237 # define SDVOB_HOTPLUG_INT_EN (1 << 26) 1238 # define SDVOC_HOTPLUG_INT_EN (1 << 25) 1239 # define TV_HOTPLUG_INT_EN (1 << 18) 1240 # define CRT_HOTPLUG_INT_EN (1 << 9) 1241 # define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 1242 /* must use period 64 on GM45 according to docs */ 1243 # define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 1244 # define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 1245 # define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 1246 # define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 1247 # define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 1248 # define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 1249 # define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 1250 # define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 1251 # define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 1252 # define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 1253 # define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 1254 # define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 1255 # define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 1256 # define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */ 1257 1258 #define PORT_HOTPLUG_STAT 0x61114 1259 # define HDMIB_HOTPLUG_INT_STATUS (1 << 29) 1260 # define HDMIC_HOTPLUG_INT_STATUS (1 << 28) 1261 # define HDMID_HOTPLUG_INT_STATUS (1 << 27) 1262 # define CRT_HOTPLUG_INT_STATUS (1 << 11) 1263 # define TV_HOTPLUG_INT_STATUS (1 << 10) 1264 # define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 1265 # define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 1266 # define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 1267 # define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 1268 # define SDVOC_HOTPLUG_INT_STATUS (1 << 7) 1269 # define SDVOB_HOTPLUG_INT_STATUS (1 << 6) 1270 1271 #define SDVOB 0x61140 1272 #define SDVOC 0x61160 1273 #define SDVO_ENABLE (1 << 31) 1274 #define SDVO_PIPE_B_SELECT (1 << 30) 1275 #define SDVO_STALL_SELECT (1 << 29) 1276 #define SDVO_INTERRUPT_ENABLE (1 << 26) 1277 1278 #define DISPLAY_HOTPLUG_CTL 0x61164 1279 /* 1280 * 915G/GM SDVO pixel multiplier. 1281 * 1282 * Programmed value is multiplier - 1, up to 5x. 1283 * 1284 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 1285 */ 1286 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 1287 #define SDVO_PORT_MULTIPLY_SHIFT 23 1288 #define SDVO_PHASE_SELECT_MASK (15 << 19) 1289 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 1290 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 1291 #define SDVOC_GANG_MODE (1 << 16) 1292 #define SDVO_ENCODING_SDVO (0x0 << 10) 1293 #define SDVO_ENCODING_HDMI (0x2 << 10) 1294 /* Requird for HDMI operation */ 1295 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) 1296 #define SDVO_BORDER_ENABLE (1 << 7) 1297 #define SDVO_AUDIO_ENABLE (1 << 6) 1298 /* New with 965, default is to be set */ 1299 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 1300 /* New with 965, default is to be set */ 1301 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 1302 /* 915/945 only, read-only bit */ 1303 #define SDVOB_PCIE_CONCURRENCY (1 << 3) 1304 #define SDVO_DETECTED (1 << 2) 1305 /* Bits to be preserved when writing */ 1306 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14)) 1307 #define SDVOC_PRESERVE_MASK (1 << 17) 1308 1309 #define UDIB_SVB_SHB_CODES 0x61144 1310 #define UDIB_SHA_BLANK_CODES 0x61148 1311 #define UDIB_START_END_FILL_CODES 0x6114c 1312 1313 1314 #define SDVOUDI 0x61150 1315 1316 #define I830_HTOTAL_MASK 0xfff0000 1317 #define I830_HACTIVE_MASK 0x7ff 1318 1319 #define I830_HBLANKEND_MASK 0xfff0000 1320 #define I830_HBLANKSTART_MASK 0xfff 1321 1322 #define I830_HSYNCEND_MASK 0xfff0000 1323 #define I830_HSYNCSTART_MASK 0xfff 1324 1325 #define I830_VTOTAL_MASK 0xfff0000 1326 #define I830_VACTIVE_MASK 0x7ff 1327 1328 #define I830_VBLANKEND_MASK 0xfff0000 1329 #define I830_VBLANKSTART_MASK 0xfff 1330 1331 #define I830_VSYNCEND_MASK 0xfff0000 1332 #define I830_VSYNCSTART_MASK 0xfff 1333 1334 #define I830_PIPEA_HORZ_MASK 0x7ff0000 1335 #define I830_PIPEA_VERT_MASK 0x7ff 1336 1337 #define ADPA 0x61100 1338 #define ADPA_DAC_ENABLE (1<<31) 1339 #define ADPA_DAC_DISABLE 0 1340 #define ADPA_PIPE_SELECT_MASK (1<<30) 1341 #define ADPA_PIPE_A_SELECT 0 1342 #define ADPA_PIPE_B_SELECT (1<<30) 1343 #define ADPA_USE_VGA_HVPOLARITY (1<<15) 1344 #define ADPA_SETS_HVPOLARITY 0 1345 #define ADPA_VSYNC_CNTL_DISABLE (1<<11) 1346 #define ADPA_VSYNC_CNTL_ENABLE 0 1347 #define ADPA_HSYNC_CNTL_DISABLE (1<<10) 1348 #define ADPA_HSYNC_CNTL_ENABLE 0 1349 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 1350 #define ADPA_VSYNC_ACTIVE_LOW 0 1351 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 1352 #define ADPA_HSYNC_ACTIVE_LOW 0 1353 1354 #define PCH_DSP_CHICKEN1 0x42000 1355 #define PCH_DSP_CHICKEN2 0x42004 1356 #define PCH_DSP_CHICKEN3 0x4200c 1357 #define PCH_DSPCLK_GATE_D 0x42020 1358 #define PCH_DSPRAMCLK_GATE_D 0x42024 1359 #define PCH_3DCGDIS0 0x46020 1360 #define PCH_3DCGDIS1 0x46024 1361 #define PCH_3DRAMCGDIS0 0x46028 1362 #define SOUTH_DSPCLK_GATE_D 0xc2020 1363 1364 #define CPU_eDP_A 0x64000 1365 #define PCH_DP_B 0xe4100 1366 #define PCH_DP_C 0xe4200 1367 #define PCH_DP_D 0xe4300 1368 1369 #define DVOA 0x61120 1370 #define DVOB 0x61140 1371 #define DVOC 0x61160 1372 #define DVO_ENABLE (1 << 31) 1373 #define DVO_PIPE_B_SELECT (1 << 30) 1374 #define DVO_PIPE_STALL_UNUSED (0 << 28) 1375 #define DVO_PIPE_STALL (1 << 28) 1376 #define DVO_PIPE_STALL_TV (2 << 28) 1377 #define DVO_PIPE_STALL_MASK (3 << 28) 1378 #define DVO_USE_VGA_SYNC (1 << 15) 1379 #define DVO_DATA_ORDER_I740 (0 << 14) 1380 #define DVO_DATA_ORDER_FP (1 << 14) 1381 #define DVO_VSYNC_DISABLE (1 << 11) 1382 #define DVO_HSYNC_DISABLE (1 << 10) 1383 #define DVO_VSYNC_TRISTATE (1 << 9) 1384 #define DVO_HSYNC_TRISTATE (1 << 8) 1385 #define DVO_BORDER_ENABLE (1 << 7) 1386 #define DVO_DATA_ORDER_GBRG (1 << 6) 1387 #define DVO_DATA_ORDER_RGGB (0 << 6) 1388 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 1389 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 1390 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 1391 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 1392 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 1393 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 1394 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 1395 #define DVO_PRESERVE_MASK (0x7<<24) 1396 1397 #define DVOA_SRCDIM 0x61124 1398 #define DVOB_SRCDIM 0x61144 1399 #define DVOC_SRCDIM 0x61164 1400 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 1401 #define DVO_SRCDIM_VERTICAL_SHIFT 0 1402 1403 /* @defgroup LVDS 1404 * @{ 1405 */ 1406 /* 1407 * This register controls the LVDS output enable, pipe selection, and data 1408 * format selection. 1409 * 1410 * All of the clock/data pairs are force powered down by power sequencing. 1411 */ 1412 #define LVDS 0x61180 1413 /* 1414 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 1415 * the DPLL semantics change when the LVDS is assigned to that pipe. 1416 */ 1417 # define LVDS_PORT_EN (1 << 31) 1418 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 1419 # define LVDS_PIPEB_SELECT (1 << 30) 1420 1421 /* on 965, dithering is enabled in this register, not PFIT_CONTROL */ 1422 # define LVDS_DITHER_ENABLE (1 << 25) 1423 1424 /* 1425 * Selects between .0 and .1 formats: 1426 * 1427 * 0 = 1x18.0, 2x18.0, 1x24.0 or 2x24.0 1428 * 1 = 1x24.1 or 2x24.1 1429 */ 1430 # define LVDS_DATA_FORMAT_DOT_ONE (1 << 24) 1431 1432 /* Using LE instead of HS on second channel control signal */ 1433 # define LVDS_LE_CONTROL_ENABLE (1 << 23) 1434 1435 /* Using LF instead of VS on second channel control signal */ 1436 # define LVDS_LF_CONTROL_ENABLE (1 << 22) 1437 1438 /* invert vsync signal polarity */ 1439 # define LVDS_VSYNC_POLARITY_INVERT (1 << 21) 1440 1441 /* invert hsync signal polarity */ 1442 # define LVDS_HSYNC_POLARITY_INVERT (1 << 20) 1443 1444 /* invert display enable signal polarity */ 1445 # define LVDS_DE_POLARITY_INVERT (1 << 19) 1446 1447 /* 1448 * Control signals for second channel, ignored in single channel modes 1449 */ 1450 1451 /* send DE, HS, VS on second channel */ 1452 # define LVDS_SECOND_CHANNEL_DE_HS_VS (0 << 17) 1453 1454 # define LVDS_SECOND_CHANNEL_RESERVED (1 << 17) 1455 1456 /* Send zeros instead of DE, HS, VS on second channel */ 1457 # define LVDS_SECOND_CHANNEL_ZEROS (2 << 17) 1458 1459 /* Set DE=0, HS=LE, VS=LF on second channel */ 1460 # define LVDS_SECOND_CHANNEL_HS_VS (3 << 17) 1461 1462 /* 1463 * Send duplicate data for channel reserved bits, otherwise send zeros 1464 */ 1465 # define LVDS_CHANNEL_DUP_RESERVED (1 << 16) 1466 1467 /* 1468 * Enable border for unscaled (or aspect-scaled) display 1469 */ 1470 # define LVDS_BORDER_ENABLE (1 << 15) 1471 1472 /* 1473 * Tri-state the LVDS buffers when powered down, otherwise 1474 * they are set to 0V 1475 */ 1476 # define LVDS_POWER_DOWN_TRI_STATE (1 << 10) 1477 1478 /* 1479 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 1480 * pixel. 1481 */ 1482 # define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 1483 # define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 1484 # define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 1485 /* 1486 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 1487 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 1488 * on. 1489 */ 1490 # define LVDS_A3_POWER_MASK (3 << 6) 1491 # define LVDS_A3_POWER_DOWN (0 << 6) 1492 # define LVDS_A3_POWER_UP (3 << 6) 1493 /* 1494 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 1495 * is set. 1496 */ 1497 # define LVDS_CLKB_POWER_MASK (3 << 4) 1498 # define LVDS_CLKB_POWER_DOWN (0 << 4) 1499 # define LVDS_CLKB_POWER_UP (3 << 4) 1500 1501 /* 1502 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 1503 * setting for whether we are in dual-channel mode. The B3 pair will 1504 * additionally only be powered up when LVDS_A3_POWER_UP is set. 1505 */ 1506 # define LVDS_B0B3_POWER_MASK (3 << 2) 1507 # define LVDS_B0B3_POWER_DOWN (0 << 2) 1508 # define LVDS_B0B3_POWER_UP (3 << 2) 1509 1510 /* @} */ 1511 1512 #define DP_B 0x64100 1513 #define DPB_AUX_CH_CTL 0x64110 1514 #define DPB_AUX_CH_DATA1 0x64114 1515 #define DPB_AUX_CH_DATA2 0x64118 1516 #define DPB_AUX_CH_DATA3 0x6411c 1517 #define DPB_AUX_CH_DATA4 0x64120 1518 #define DPB_AUX_CH_DATA5 0x64124 1519 1520 #define DP_C 0x64200 1521 #define DPC_AUX_CH_CTL 0x64210 1522 #define DPC_AUX_CH_DATA1 0x64214 1523 #define DPC_AUX_CH_DATA2 0x64218 1524 #define DPC_AUX_CH_DATA3 0x6421c 1525 #define DPC_AUX_CH_DATA4 0x64220 1526 #define DPC_AUX_CH_DATA5 0x64224 1527 1528 #define DP_D 0x64300 1529 #define DPD_AUX_CH_CTL 0x64310 1530 #define DPD_AUX_CH_DATA1 0x64314 1531 #define DPD_AUX_CH_DATA2 0x64318 1532 #define DPD_AUX_CH_DATA3 0x6431c 1533 #define DPD_AUX_CH_DATA4 0x64320 1534 #define DPD_AUX_CH_DATA5 0x64324 1535 1536 /* 1537 * Two channel clock control. Turn this on if you need clkb for two channel mode 1538 * Overridden by global LVDS power sequencing 1539 */ 1540 1541 /* clkb off */ 1542 # define LVDS_CLKB_POWER_DOWN (0 << 4) 1543 1544 /* powered up, but clkb forced to 0 */ 1545 # define LVDS_CLKB_POWER_PARTIAL (1 << 4) 1546 1547 /* clock B running */ 1548 # define LVDS_CLKB_POWER_UP (3 << 4) 1549 1550 /* 1551 * Two channel mode B0-B2 control. Sets state when power is on. 1552 * Set to POWER_DOWN in single channel mode, other settings enable 1553 * two channel mode. The CLKB power control controls whether that clock 1554 * is enabled during two channel mode. 1555 * 1556 */ 1557 /* Everything is off, including B3 and CLKB */ 1558 # define LVDS_B_POWER_DOWN (0 << 2) 1559 1560 /* B0, B1, B2 and data lines forced to 0. timing is active */ 1561 # define LVDS_B_POWER_PARTIAL (1 << 2) 1562 1563 /* data lines active (both timing and colour) */ 1564 # define LVDS_B_POWER_UP (3 << 2) 1565 1566 /* @defgroup TV_CTL 1567 * @{ 1568 */ 1569 #define TV_CTL 0x68000 1570 /* Enables the TV encoder */ 1571 # define TV_ENC_ENABLE (1 << 31) 1572 /* Sources the TV encoder input from pipe B instead of A. */ 1573 # define TV_ENC_PIPEB_SELECT (1 << 30) 1574 /* Outputs composite video (DAC A only) */ 1575 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 1576 /* Outputs SVideo video (DAC B/C) */ 1577 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 1578 /* Outputs Component video (DAC A/B/C) */ 1579 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 1580 /* Outputs Composite and SVideo (DAC A/B/C) */ 1581 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 1582 # define TV_TRILEVEL_SYNC (1 << 21) 1583 /* Enables slow sync generation (945GM only) */ 1584 # define TV_SLOW_SYNC (1 << 20) 1585 /* Selects 4x oversampling for 480i and 576p */ 1586 # define TV_OVERSAMPLE_4X (0 << 18) 1587 /* Selects 2x oversampling for 720p and 1080i */ 1588 # define TV_OVERSAMPLE_2X (1 << 18) 1589 /* Selects no oversampling for 1080p */ 1590 # define TV_OVERSAMPLE_NONE (2 << 18) 1591 /* Selects 8x oversampling */ 1592 # define TV_OVERSAMPLE_8X (3 << 18) 1593 /* Selects progressive mode rather than interlaced */ 1594 # define TV_PROGRESSIVE (1 << 17) 1595 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 1596 # define TV_PAL_BURST (1 << 16) 1597 /* Field for setting delay of Y compared to C */ 1598 # define TV_YC_SKEW_MASK (7 << 12) 1599 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 1600 # define TV_ENC_SDP_FIX (1 << 11) 1601 /* 1602 * Enables a fix for the 915GM only. 1603 * 1604 * Not sure what it does. 1605 */ 1606 # define TV_ENC_C0_FIX (1 << 10) 1607 /* Bits that must be preserved by software */ 1608 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 1609 # define TV_FUSE_STATE_MASK (3 << 4) 1610 /* Read-only state that reports all features enabled */ 1611 # define TV_FUSE_STATE_ENABLED (0 << 4) 1612 /* Read-only state that reports that Macrovision is disabled in hardware*/ 1613 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 1614 /* Read-only state that reports that TV-out is disabled in hardware. */ 1615 # define TV_FUSE_STATE_DISABLED (2 << 4) 1616 /* Normal operation */ 1617 # define TV_TEST_MODE_NORMAL (0 << 0) 1618 /* Encoder test pattern 1 - combo pattern */ 1619 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 1620 /* Encoder test pattern 2 - full screen vertical 75% color bars */ 1621 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 1622 /* Encoder test pattern 3 - full screen horizontal 75% color bars */ 1623 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 1624 /* Encoder test pattern 4 - random noise */ 1625 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 1626 /* Encoder test pattern 5 - linear color ramps */ 1627 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 1628 /* 1629 * This test mode forces the DACs to 50% of full output. 1630 * 1631 * This is used for load detection in combination with TVDAC_SENSE_MASK 1632 */ 1633 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 1634 # define TV_TEST_MODE_MASK (7 << 0) 1635 /* @} */ 1636 1637 /* @defgroup TV_DAC 1638 * @{ 1639 */ 1640 #define TV_DAC 0x68004 1641 /* 1642 * Reports that DAC state change logic has reported change (RO). 1643 * 1644 * This gets cleared when TV_DAC_STATE_EN is cleared 1645 */ 1646 # define TVDAC_STATE_CHG (1 << 31) 1647 # define TVDAC_SENSE_MASK (7 << 28) 1648 /* Reports that DAC A voltage is above the detect threshold */ 1649 # define TVDAC_A_SENSE (1 << 30) 1650 /* Reports that DAC B voltage is above the detect threshold */ 1651 # define TVDAC_B_SENSE (1 << 29) 1652 /* Reports that DAC C voltage is above the detect threshold */ 1653 # define TVDAC_C_SENSE (1 << 28) 1654 /* 1655 * Enables DAC state detection logic, for load-based TV detection. 1656 * 1657 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 1658 * to off, for load detection to work. 1659 */ 1660 # define TVDAC_STATE_CHG_EN (1 << 27) 1661 /* Sets the DAC A sense value to high */ 1662 # define TVDAC_A_SENSE_CTL (1 << 26) 1663 /* Sets the DAC B sense value to high */ 1664 # define TVDAC_B_SENSE_CTL (1 << 25) 1665 /* Sets the DAC C sense value to high */ 1666 # define TVDAC_C_SENSE_CTL (1 << 24) 1667 /* Overrides the ENC_ENABLE and DAC voltage levels */ 1668 # define DAC_CTL_OVERRIDE (1 << 7) 1669 /* Sets the slew rate. Must be preserved in software */ 1670 # define ENC_TVDAC_SLEW_FAST (1 << 6) 1671 # define DAC_A_1_3_V (0 << 4) 1672 # define DAC_A_1_1_V (1 << 4) 1673 # define DAC_A_0_7_V (2 << 4) 1674 # define DAC_A_OFF (3 << 4) 1675 # define DAC_B_1_3_V (0 << 2) 1676 # define DAC_B_1_1_V (1 << 2) 1677 # define DAC_B_0_7_V (2 << 2) 1678 # define DAC_B_OFF (3 << 2) 1679 # define DAC_C_1_3_V (0 << 0) 1680 # define DAC_C_1_1_V (1 << 0) 1681 # define DAC_C_0_7_V (2 << 0) 1682 # define DAC_C_OFF (3 << 0) 1683 /* @} */ 1684 1685 /* 1686 * CSC coefficients are stored in a floating point format with 9 bits of 1687 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2*-n, 1688 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 1689 * -1 (0x3) being the only legal negative value. 1690 */ 1691 #define TV_CSC_Y 0x68010 1692 # define TV_RY_MASK 0x07ff0000 1693 # define TV_RY_SHIFT 16 1694 # define TV_GY_MASK 0x00000fff 1695 # define TV_GY_SHIFT 0 1696 1697 #define TV_CSC_Y2 0x68014 1698 # define TV_BY_MASK 0x07ff0000 1699 # define TV_BY_SHIFT 16 1700 /* 1701 * Y attenuation for component video. 1702 * 1703 * Stored in 1.9 fixed point. 1704 */ 1705 # define TV_AY_MASK 0x000003ff 1706 # define TV_AY_SHIFT 0 1707 1708 #define TV_CSC_U 0x68018 1709 # define TV_RU_MASK 0x07ff0000 1710 # define TV_RU_SHIFT 16 1711 # define TV_GU_MASK 0x000007ff 1712 # define TV_GU_SHIFT 0 1713 1714 #define TV_CSC_U2 0x6801c 1715 # define TV_BU_MASK 0x07ff0000 1716 # define TV_BU_SHIFT 16 1717 /* 1718 * U attenuation for component video. 1719 * 1720 * Stored in 1.9 fixed point. 1721 */ 1722 # define TV_AU_MASK 0x000003ff 1723 # define TV_AU_SHIFT 0 1724 1725 #define TV_CSC_V 0x68020 1726 # define TV_RV_MASK 0x0fff0000 1727 # define TV_RV_SHIFT 16 1728 # define TV_GV_MASK 0x000007ff 1729 # define TV_GV_SHIFT 0 1730 1731 #define TV_CSC_V2 0x68024 1732 # define TV_BV_MASK 0x07ff0000 1733 # define TV_BV_SHIFT 16 1734 /* 1735 * V attenuation for component video. 1736 * 1737 * Stored in 1.9 fixed point. 1738 */ 1739 # define TV_AV_MASK 0x000007ff 1740 # define TV_AV_SHIFT 0 1741 1742 /* @defgroup TV_CSC_KNOBS 1743 * @{ 1744 */ 1745 #define TV_CLR_KNOBS 0x68028 1746 /* 2s-complement brightness adjustment */ 1747 # define TV_BRIGHTNESS_MASK 0xff000000 1748 # define TV_BRIGHTNESS_SHIFT 24 1749 /* Contrast adjustment, as a 2.6 unsigned floating point number */ 1750 # define TV_CONTRAST_MASK 0x00ff0000 1751 # define TV_CONTRAST_SHIFT 16 1752 /* Saturation adjustment, as a 2.6 unsigned floating point number */ 1753 # define TV_SATURATION_MASK 0x0000ff00 1754 # define TV_SATURATION_SHIFT 8 1755 /* Hue adjustment, as an integer phase angle in degrees */ 1756 # define TV_HUE_MASK 0x000000ff 1757 # define TV_HUE_SHIFT 0 1758 /* @} */ 1759 1760 /* @defgroup TV_CLR_LEVEL 1761 * @{ 1762 */ 1763 #define TV_CLR_LEVEL 0x6802c 1764 /* Controls the DAC level for black */ 1765 # define TV_BLACK_LEVEL_MASK 0x01ff0000 1766 # define TV_BLACK_LEVEL_SHIFT 16 1767 /* Controls the DAC level for blanking */ 1768 # define TV_BLANK_LEVEL_MASK 0x000001ff 1769 # define TV_BLANK_LEVEL_SHIFT 0 1770 /* @} */ 1771 1772 /* @defgroup TV_H_CTL_1 1773 * @{ 1774 */ 1775 #define TV_H_CTL_1 0x68030 1776 /* Number of pixels in the hsync. */ 1777 # define TV_HSYNC_END_MASK 0x1fff0000 1778 # define TV_HSYNC_END_SHIFT 16 1779 /* Total number of pixels minus one in the line (display and blanking). */ 1780 # define TV_HTOTAL_MASK 0x00001fff 1781 # define TV_HTOTAL_SHIFT 0 1782 /* @} */ 1783 1784 /* @defgroup TV_H_CTL_2 1785 * @{ 1786 */ 1787 #define TV_H_CTL_2 0x68034 1788 /* Enables the colorburst (needed for non-component color) */ 1789 # define TV_BURST_ENA (1 << 31) 1790 /* Offset of the colorburst from the start of hsync, in pixels minus one. */ 1791 # define TV_HBURST_START_SHIFT 16 1792 # define TV_HBURST_START_MASK 0x1fff0000 1793 /* Length of the colorburst */ 1794 # define TV_HBURST_LEN_SHIFT 0 1795 # define TV_HBURST_LEN_MASK 0x0001fff 1796 /* @} */ 1797 1798 /* @defgroup TV_H_CTL_3 1799 * @{ 1800 */ 1801 #define TV_H_CTL_3 0x68038 1802 /* End of hblank, measured in pixels minus one from start of hsync */ 1803 # define TV_HBLANK_END_SHIFT 16 1804 # define TV_HBLANK_END_MASK 0x1fff0000 1805 /* Start of hblank, measured in pixels minus one from start of hsync */ 1806 # define TV_HBLANK_START_SHIFT 0 1807 # define TV_HBLANK_START_MASK 0x0001fff 1808 /* @} */ 1809 1810 /* @defgroup TV_V_CTL_1 1811 * @{ 1812 */ 1813 #define TV_V_CTL_1 0x6803c 1814 /* XXX */ 1815 # define TV_NBR_END_SHIFT 16 1816 # define TV_NBR_END_MASK 0x07ff0000 1817 /* XXX */ 1818 # define TV_VI_END_F1_SHIFT 8 1819 # define TV_VI_END_F1_MASK 0x00003f00 1820 /* XXX */ 1821 # define TV_VI_END_F2_SHIFT 0 1822 # define TV_VI_END_F2_MASK 0x0000003f 1823 /* @} */ 1824 1825 /* @defgroup TV_V_CTL_2 1826 * @{ 1827 */ 1828 #define TV_V_CTL_2 0x68040 1829 /* Length of vsync, in half lines */ 1830 # define TV_VSYNC_LEN_MASK 0x07ff0000 1831 # define TV_VSYNC_LEN_SHIFT 16 1832 /* Offset of the start of vsync in field 1, measured in one less than the 1833 * number of half lines. 1834 */ 1835 # define TV_VSYNC_START_F1_MASK 0x00007f00 1836 # define TV_VSYNC_START_F1_SHIFT 8 1837 /* 1838 * Offset of the start of vsync in field 2, measured in one less than the 1839 * number of half lines. 1840 */ 1841 # define TV_VSYNC_START_F2_MASK 0x0000007f 1842 # define TV_VSYNC_START_F2_SHIFT 0 1843 /* @} */ 1844 1845 /* @defgroup TV_V_CTL_3 1846 * @{ 1847 */ 1848 #define TV_V_CTL_3 0x68044 1849 /* Enables generation of the equalization signal */ 1850 # define TV_EQUAL_ENA (1 << 31) 1851 /* Length of vsync, in half lines */ 1852 # define TV_VEQ_LEN_MASK 0x007f0000 1853 # define TV_VEQ_LEN_SHIFT 16 1854 /* Offset of the start of equalization in field 1, measured in one less than 1855 * the number of half lines. 1856 */ 1857 # define TV_VEQ_START_F1_MASK 0x0007f00 1858 # define TV_VEQ_START_F1_SHIFT 8 1859 /* 1860 * Offset of the start of equalization in field 2, measured in one less than 1861 * the number of half lines. 1862 */ 1863 # define TV_VEQ_START_F2_MASK 0x000007f 1864 # define TV_VEQ_START_F2_SHIFT 0 1865 /* @} */ 1866 1867 /* @defgroup TV_V_CTL_4 1868 * @{ 1869 */ 1870 #define TV_V_CTL_4 0x68048 1871 /* 1872 * Offset to start of vertical colorburst, measured in one less than the 1873 * number of lines from vertical start. 1874 */ 1875 # define TV_VBURST_START_F1_MASK 0x003f0000 1876 # define TV_VBURST_START_F1_SHIFT 16 1877 /* 1878 * Offset to the end of vertical colorburst, measured in one less than the 1879 * number of lines from the start of NBR. 1880 */ 1881 # define TV_VBURST_END_F1_MASK 0x000000ff 1882 # define TV_VBURST_END_F1_SHIFT 0 1883 /* @} */ 1884 1885 /* @defgroup TV_V_CTL_5 1886 * @{ 1887 */ 1888 #define TV_V_CTL_5 0x6804c 1889 /* 1890 * Offset to start of vertical colorburst, measured in one less than the 1891 * number of lines from vertical start. 1892 */ 1893 # define TV_VBURST_START_F2_MASK 0x003f0000 1894 # define TV_VBURST_START_F2_SHIFT 16 1895 /* 1896 * Offset to the end of vertical colorburst, measured in one less than the 1897 * number of lines from the start of NBR. 1898 */ 1899 # define TV_VBURST_END_F2_MASK 0x000000ff 1900 # define TV_VBURST_END_F2_SHIFT 0 1901 /* @} */ 1902 1903 /* @defgroup TV_V_CTL_6 1904 * @{ 1905 */ 1906 #define TV_V_CTL_6 0x68050 1907 /* 1908 * Offset to start of vertical colorburst, measured in one less than the 1909 * number of lines from vertical start. 1910 */ 1911 # define TV_VBURST_START_F3_MASK 0x003f0000 1912 # define TV_VBURST_START_F3_SHIFT 16 1913 /* 1914 * Offset to the end of vertical colorburst, measured in one less than the 1915 * number of lines from the start of NBR. 1916 */ 1917 # define TV_VBURST_END_F3_MASK 0x000000ff 1918 # define TV_VBURST_END_F3_SHIFT 0 1919 /* @} */ 1920 1921 /* @defgroup TV_V_CTL_7 1922 * @{ 1923 */ 1924 #define TV_V_CTL_7 0x68054 1925 /* 1926 * Offset to start of vertical colorburst, measured in one less than the 1927 * number of lines from vertical start. 1928 */ 1929 # define TV_VBURST_START_F4_MASK 0x003f0000 1930 # define TV_VBURST_START_F4_SHIFT 16 1931 /* 1932 * Offset to the end of vertical colorburst, measured in one less than the 1933 * number of lines from the start of NBR. 1934 */ 1935 # define TV_VBURST_END_F4_MASK 0x000000ff 1936 # define TV_VBURST_END_F4_SHIFT 0 1937 /* @} */ 1938 1939 /* @defgroup TV_SC_CTL_1 1940 * @{ 1941 */ 1942 #define TV_SC_CTL_1 0x68060 1943 /* Turns on the first subcarrier phase generation DDA */ 1944 # define TV_SC_DDA1_EN (1 << 31) 1945 /* Turns on the first subcarrier phase generation DDA */ 1946 # define TV_SC_DDA2_EN (1 << 30) 1947 /* Turns on the first subcarrier phase generation DDA */ 1948 # define TV_SC_DDA3_EN (1 << 29) 1949 /* Sets the subcarrier DDA to reset frequency every other field */ 1950 # define TV_SC_RESET_EVERY_2 (0 << 24) 1951 /* Sets the subcarrier DDA to reset frequency every fourth field */ 1952 # define TV_SC_RESET_EVERY_4 (1 << 24) 1953 /* Sets the subcarrier DDA to reset frequency every eighth field */ 1954 # define TV_SC_RESET_EVERY_8 (2 << 24) 1955 /* Sets the subcarrier DDA to never reset the frequency */ 1956 # define TV_SC_RESET_NEVER (3 << 24) 1957 /* Sets the peak amplitude of the colorburst.*/ 1958 # define TV_BURST_LEVEL_MASK 0x00ff0000 1959 # define TV_BURST_LEVEL_SHIFT 16 1960 /* Sets the increment of the first subcarrier phase generation DDA */ 1961 # define TV_SCDDA1_INC_MASK 0x00000fff 1962 # define TV_SCDDA1_INC_SHIFT 0 1963 /* @} */ 1964 1965 /* @defgroup TV_SC_CTL_2 1966 * @{ 1967 */ 1968 #define TV_SC_CTL_2 0x68064 1969 /* Sets the rollover for the second subcarrier phase generation DDA */ 1970 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 1971 # define TV_SCDDA2_SIZE_SHIFT 16 1972 /* Sets the increent of the second subcarrier phase generation DDA */ 1973 # define TV_SCDDA2_INC_MASK 0x00007fff 1974 # define TV_SCDDA2_INC_SHIFT 0 1975 /* @} */ 1976 1977 /* @defgroup TV_SC_CTL_3 1978 * @{ 1979 */ 1980 #define TV_SC_CTL_3 0x68068 1981 /* Sets the rollover for the third subcarrier phase generation DDA */ 1982 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 1983 # define TV_SCDDA3_SIZE_SHIFT 16 1984 /* Sets the increent of the third subcarrier phase generation DDA */ 1985 # define TV_SCDDA3_INC_MASK 0x00007fff 1986 # define TV_SCDDA3_INC_SHIFT 0 1987 /* @} */ 1988 1989 /* @defgroup TV_WIN_POS 1990 * @{ 1991 */ 1992 #define TV_WIN_POS 0x68070 1993 /* X coordinate of the display from the start of horizontal active */ 1994 # define TV_XPOS_MASK 0x1fff0000 1995 # define TV_XPOS_SHIFT 16 1996 /* Y coordinate of the display from the start of vertical active (NBR) */ 1997 # define TV_YPOS_MASK 0x00000fff 1998 # define TV_YPOS_SHIFT 0 1999 /* @} */ 2000 2001 /* @defgroup TV_WIN_SIZE 2002 * @{ 2003 */ 2004 #define TV_WIN_SIZE 0x68074 2005 /* Horizontal size of the display window, measured in pixels*/ 2006 # define TV_XSIZE_MASK 0x1fff0000 2007 # define TV_XSIZE_SHIFT 16 2008 /* 2009 * Vertical size of the display window, measured in pixels. 2010 * 2011 * Must be even for interlaced modes. 2012 */ 2013 # define TV_YSIZE_MASK 0x00000fff 2014 # define TV_YSIZE_SHIFT 0 2015 /* @} */ 2016 2017 /* @defgroup TV_FILTER_CTL_1 2018 * @{ 2019 */ 2020 #define TV_FILTER_CTL_1 0x68080 2021 /* 2022 * Enables automatic scaling calculation. 2023 * 2024 * If set, the rest of the registers are ignored, and the calculated values can 2025 * be read back from the register. 2026 */ 2027 # define TV_AUTO_SCALE (1 << 31) 2028 /* 2029 * Disables the vertical filter. 2030 * 2031 * This is required on modes more than 1024 pixels wide */ 2032 # define TV_V_FILTER_BYPASS (1 << 29) 2033 /* Enables adaptive vertical filtering */ 2034 # define TV_VADAPT (1 << 28) 2035 # define TV_VADAPT_MODE_MASK (3 << 26) 2036 /* Selects the least adaptive vertical filtering mode */ 2037 # define TV_VADAPT_MODE_LEAST (0 << 26) 2038 /* Selects the moderately adaptive vertical filtering mode */ 2039 # define TV_VADAPT_MODE_MODERATE (1 << 26) 2040 /* Selects the most adaptive vertical filtering mode */ 2041 # define TV_VADAPT_MODE_MOST (3 << 26) 2042 /* 2043 * Sets the horizontal scaling factor. 2044 * 2045 * This should be the fractional part of the horizontal scaling factor divided 2046 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 2047 * 2048 * (src width - 1) / ((oversample * dest width) - 1) 2049 */ 2050 # define TV_HSCALE_FRAC_MASK 0x00003fff 2051 # define TV_HSCALE_FRAC_SHIFT 0 2052 /* @} */ 2053 2054 /* @defgroup TV_FILTER_CTL_2 2055 * @{ 2056 */ 2057 #define TV_FILTER_CTL_2 0x68084 2058 /* 2059 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 2060 * 2061 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 2062 */ 2063 # define TV_VSCALE_INT_MASK 0x00038000 2064 # define TV_VSCALE_INT_SHIFT 15 2065 /* 2066 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 2067 * 2068 * \sa TV_VSCALE_INT_MASK 2069 */ 2070 # define TV_VSCALE_FRAC_MASK 0x00007fff 2071 # define TV_VSCALE_FRAC_SHIFT 0 2072 /* @} */ 2073 2074 /* @defgroup TV_FILTER_CTL_3 2075 * @{ 2076 */ 2077 #define TV_FILTER_CTL_3 0x68088 2078 /* 2079 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 2080 * 2081 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 2082 * 2083 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 2084 */ 2085 # define TV_VSCALE_IP_INT_MASK 0x00038000 2086 # define TV_VSCALE_IP_INT_SHIFT 15 2087 /* 2088 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 2089 * 2090 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 2091 * 2092 * \sa TV_VSCALE_IP_INT_MASK 2093 */ 2094 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 2095 # define TV_VSCALE_IP_FRAC_SHIFT 0 2096 /* @} */ 2097 2098 /* @defgroup TV_CC_CONTROL 2099 * @{ 2100 */ 2101 #define TV_CC_CONTROL 0x68090 2102 # define TV_CC_ENABLE (1 << 31) 2103 /* 2104 * Specifies which field to send the CC data in. 2105 * 2106 * CC data is usually sent in field 0. 2107 */ 2108 # define TV_CC_FID_MASK (1 << 27) 2109 # define TV_CC_FID_SHIFT 27 2110 /* Sets the horizontal position of the CC data. Usually 135. */ 2111 # define TV_CC_HOFF_MASK 0x03ff0000 2112 # define TV_CC_HOFF_SHIFT 16 2113 /* Sets the vertical position of the CC data. Usually 21 */ 2114 # define TV_CC_LINE_MASK 0x0000003f 2115 # define TV_CC_LINE_SHIFT 0 2116 /* @} */ 2117 2118 /* @defgroup TV_CC_DATA 2119 * @{ 2120 */ 2121 #define TV_CC_DATA 0x68094 2122 # define TV_CC_RDY (1 << 31) 2123 /* Second word of CC data to be transmitted. */ 2124 # define TV_CC_DATA_2_MASK 0x007f0000 2125 # define TV_CC_DATA_2_SHIFT 16 2126 /* First word of CC data to be transmitted. */ 2127 # define TV_CC_DATA_1_MASK 0x0000007f 2128 # define TV_CC_DATA_1_SHIFT 0 2129 /* @} 2130 */ 2131 2132 /* @{ */ 2133 #define TV_H_LUMA_0 0x68100 2134 #define TV_H_LUMA_59 0x681ec 2135 #define TV_H_CHROMA_0 0x68200 2136 #define TV_H_CHROMA_59 0x682ec 2137 #define TV_V_LUMA_0 0x68300 2138 #define TV_V_LUMA_42 0x683a8 2139 #define TV_V_CHROMA_0 0x68400 2140 #define TV_V_CHROMA_42 0x684a8 2141 /* @} */ 2142 2143 #define PIPEA_DSL 0x70000 2144 2145 #define PIPEACONF 0x70008 2146 #define PIPEACONF_ENABLE (1<<31) 2147 #define PIPEACONF_DISABLE 0 2148 #define PIPEACONF_DOUBLE_WIDE (1<<30) 2149 #define I965_PIPECONF_ACTIVE (1<<30) 2150 #define PIPEACONF_SINGLE_WIDE 0 2151 #define PIPEACONF_PIPE_UNLOCKED 0 2152 #define PIPEACONF_PIPE_LOCKED (1<<25) 2153 #define PIPEACONF_PALETTE 0 2154 #define PIPEACONF_GAMMA (1<<24) 2155 #define PIPECONF_FORCE_BORDER (1<<25) 2156 #define PIPECONF_PROGRESSIVE (0 << 21) 2157 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 2158 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 2159 /* ironlake: gamma */ 2160 #define PIPECONF_PALETTE_8BIT (0<<24) 2161 #define PIPECONF_PALETTE_10BIT (1<<24) 2162 #define PIPECONF_PALETTE_12BIT (2<<24) 2163 #define PIPECONF_FORCE_BORDER (1<<25) 2164 #define PIPECONF_PROGRESSIVE (0 << 21) 2165 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 2166 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 2167 /* ironlake */ 2168 #define PIPECONF_MSA_TIMING_DELAY (0<<18) /* for eDP */ 2169 #define PIPECONF_NO_DYNAMIC_RATE_CHANGE (0 << 16) 2170 #define PIPECONF_NO_ROTATION (0<<14) 2171 #define PIPECONF_FULL_COLOR_RANGE (0<<13) 2172 #define PIPECONF_CE_COLOR_RANGE (1<<13) 2173 #define PIPECONF_COLOR_SPACE_RGB (0<<11) 2174 #define PIPECONF_COLOR_SPACE_YUV601 (1<<11) 2175 #define PIPECONF_COLOR_SPACE_YUV709 (2<<11) 2176 #define PIPECONF_CONNECT_DEFAULT (0<<9) 2177 #define PIPECONF_8BPP (0<<5) 2178 #define PIPECONF_10BPP (1<<5) 2179 #define PIPECONF_6BPP (2<<5) 2180 #define PIPECONF_12BPP (3<<5) 2181 #define PIPECONF_ENABLE_DITHER (1<<4) 2182 #define PIPECONF_DITHER_SPATIAL (0<<2) 2183 #define PIPECONF_DITHER_ST1 (1<<2) 2184 #define PIPECONF_DITHER_ST2 (2<<2) 2185 #define PIPECONF_DITHER_TEMPORAL (3<<2) 2186 2187 #define PIPEAGCMAXRED 0x70010 2188 #define PIPEAGCMAXGREEN 0x70014 2189 #define PIPEAGCMAXBLUE 0x70018 2190 #define PIPEASTAT 0x70024 2191 # define FIFO_UNDERRUN (1 << 31) 2192 # define CRC_ERROR_ENABLE (1 << 29) 2193 # define CRC_DONE_ENABLE (1 << 28) 2194 # define GMBUS_EVENT_ENABLE (1 << 27) 2195 # define VSYNC_INT_ENABLE (1 << 25) 2196 # define DLINE_COMPARE_ENABLE (1 << 24) 2197 # define DPST_EVENT_ENABLE (1 << 23) 2198 # define LBLC_EVENT_ENABLE (1 << 22) 2199 # define OFIELD_INT_ENABLE (1 << 21) 2200 # define EFIELD_INT_ENABLE (1 << 20) 2201 # define SVBLANK_INT_ENABLE (1 << 18) 2202 # define VBLANK_INT_ENABLE (1 << 17) 2203 # define OREG_UPDATE_ENABLE (1 << 16) 2204 # define CRC_ERROR_INT_STATUS (1 << 13) 2205 # define CRC_DONE_INT_STATUS (1 << 12) 2206 # define GMBUS_INT_STATUS (1 << 11) 2207 # define VSYNC_INT_STATUS (1 << 9) 2208 # define DLINE_COMPARE_STATUS (1 << 8) 2209 # define DPST_EVENT_STATUS (1 << 7) 2210 # define LBLC_EVENT_STATUS (1 << 6) 2211 # define OFIELD_INT_STATUS (1 << 5) 2212 # define EFIELD_INT_STATUS (1 << 4) 2213 # define SVBLANK_INT_STATUS (1 << 2) 2214 # define VBLANK_INT_STATUS (1 << 1) 2215 # define OREG_UPDATE_STATUS (1 << 0) 2216 2217 #define FW_BLC 0x020d8 2218 #define FW_BLC2 0x020dc 2219 #define FW_BLC_SELF 0x020e0 /* 915+ only */ 2220 2221 #define DSPARB 0x70030 2222 #define DSPARB_CSTART_SHIFT 7 2223 #define DSPARB_BSTART_SHIFT 0 2224 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 2225 #define DSPARB_AEND_SHIFT 0 2226 #define DSPFW1 0x70034 2227 #define DSPFW2 0x70038 2228 #define DSPFW3 0x7003c 2229 /* 2230 * The two pipe frame counter registers are not synchronized, so 2231 * reading a stable value is somewhat tricky. The following code 2232 * should work: 2233 * 2234 * do { 2235 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> PIPE_FRAME_HIGH_SHIFT; 2236 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> PIPE_FRAME_LOW_SHIFT); 2237 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> PIPE_FRAME_HIGH_SHIFT); 2238 * } while (high1 != high2); 2239 * frame = (high1 << 8) | low1; 2240 */ 2241 #define PIPEAFRAMEHIGH 0x70040 2242 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 2243 #define PIPE_FRAME_HIGH_SHIFT 0 2244 #define PIPEAFRAMEPIXEL 0x70044 2245 #define PIPE_FRAME_LOW_MASK 0xff000000 2246 #define PIPE_FRAME_LOW_SHIFT 24 2247 /* 2248 * Pixel within the current frame is counted in the PIPEAFRAMEPIXEL register 2249 * and is 24 bits wide. 2250 */ 2251 #define PIPE_PIXEL_MASK 0x00ffffff 2252 #define PIPE_PIXEL_SHIFT 0 2253 /* 2254 * g4x+ frame/flip counters 2255 */ 2256 #define PIPEAFRMCOUNT_G4X 0x70040 2257 #define PIPEAFLIPCOUNT_G4X 0x70044 2258 /* 2259 * Computing GMCH M and N values. 2260 * 2261 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 2262 * 2263 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 2264 * 2265 * The GMCH value is used internally 2266 */ 2267 #define PIPEA_GMCH_DATA_M 0x70050 2268 2269 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 2270 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) 2271 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 2272 2273 #define PIPE_GMCH_DATA_M_MASK (0xffffff) 2274 2275 #define PIPEA_GMCH_DATA_N 0x70054 2276 #define PIPE_GMCH_DATA_N_MASK (0xffffff) 2277 2278 /* 2279 * Computing Link M and N values. 2280 * 2281 * Link M / N = pixel_clock / ls_clk 2282 * 2283 * (the DP spec calls pixel_clock the 'strm_clk') 2284 * 2285 * The Link value is transmitted in the Main Stream 2286 * Attributes and VB-ID. 2287 */ 2288 2289 #define PIPEA_DP_LINK_M 0x70060 2290 #define PIPEA_DP_LINK_M_MASK (0xffffff) 2291 2292 #define PIPEA_DP_LINK_N 0x70064 2293 #define PIPEA_DP_LINK_N_MASK (0xffffff) 2294 2295 #define PIPEB_DSL 0x71000 2296 2297 #define PIPEBCONF 0x71008 2298 2299 #define PIPEBGCMAXRED 0x71010 2300 #define PIPEBGCMAXGREEN 0x71014 2301 #define PIPEBGCMAXBLUE 0x71018 2302 #define PIPEBSTAT 0x71024 2303 #define PIPEBFRAMEHIGH 0x71040 2304 #define PIPEBFRAMEPIXEL 0x71044 2305 #define PIPEBFRMCOUNT_G4X 0x71040 2306 #define PIPEBFLIPCOUNT_G4X 0x71044 2307 2308 #define PIPEB_GMCH_DATA_M 0x71050 2309 #define PIPEB_GMCH_DATA_N 0x71054 2310 #define PIPEB_DP_LINK_M 0x71060 2311 #define PIPEB_DP_LINK_N 0x71064 2312 2313 #define PIPEC_DSL 0x72000 2314 2315 #define PIPECCONF 0x72008 2316 2317 #define PIPECGCMAXRED 0x72010 2318 #define PIPECGCMAXGREEN 0x72014 2319 #define PIPECGCMAXBLUE 0x72018 2320 #define PIPECSTAT 0x72024 2321 #define PIPECFRMCOUNT_G4X 0x72040 2322 #define PIPECFLIPCOUNT_G4X 0x72044 2323 2324 #define PIPEC_GMCH_DATA_M 0x72050 2325 #define PIPEC_GMCH_DATA_N 0x72054 2326 #define PIPEC_DP_LINK_M 0x72060 2327 #define PIPEC_DP_LINK_N 0x72064 2328 2329 #define PIPEEDPCONF 0x7F008 2330 2331 #define DSPACNTR 0x70180 2332 #define DSPBCNTR 0x71180 2333 #define DSPCCNTR 0x72180 2334 #define DISPLAY_PLANE_ENABLE (1<<31) 2335 #define DISPLAY_PLANE_DISABLE 0 2336 #define DISPLAY_PLANE_TILED (1<<10) 2337 #define DISPPLANE_GAMMA_ENABLE (1<<30) 2338 #define DISPPLANE_GAMMA_DISABLE 0 2339 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 2340 #define DISPPLANE_8BPP (0x2<<26) 2341 #define DISPPLANE_15_16BPP (0x4<<26) 2342 #define DISPPLANE_16BPP (0x5<<26) 2343 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 2344 #define DISPPLANE_32BPP (0x7<<26) 2345 #define DISPPLANE_STEREO_ENABLE (1<<25) 2346 #define DISPPLANE_STEREO_DISABLE 0 2347 #define DISPPLANE_SEL_PIPE_MASK (1<<24) 2348 #define DISPPLANE_SEL_PIPE_A 0 2349 #define DISPPLANE_SEL_PIPE_B (1<<24) 2350 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 2351 #define DISPPLANE_SRC_KEY_DISABLE 0 2352 #define DISPPLANE_LINE_DOUBLE (1<<20) 2353 #define DISPPLANE_NO_LINE_DOUBLE 0 2354 #define DISPPLANE_STEREO_POLARITY_FIRST 0 2355 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 2356 /* plane B only */ 2357 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 2358 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 2359 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 2360 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 2361 2362 #define DSPABASE 0x70184 2363 #define DSPASTRIDE 0x70188 2364 2365 #define DSPBBASE 0x71184 2366 #define DSPBADDR DSPBBASE 2367 #define DSPBSTRIDE 0x71188 2368 2369 #define DSPCBASE 0x72184 2370 #define DSPCADDR DSPCBASE 2371 #define DSPCSTRIDE 0x72188 2372 2373 #define DSPAKEYVAL 0x70194 2374 #define DSPAKEYMASK 0x70198 2375 2376 #define DSPAPOS 0x7018C /* reserved */ 2377 #define DSPASIZE 0x70190 2378 #define DSPBPOS 0x7118C 2379 #define DSPBSIZE 0x71190 2380 2381 #define DSPASURF 0x7019C 2382 #define DSPATILEOFF 0x701A4 2383 #define DSPASURFLIVE 0x701AC 2384 2385 #define DSPBSURF 0x7119C 2386 #define DSPBTILEOFF 0x711A4 2387 #define DSPBSURFLIVE 0x711AC 2388 2389 #define DSPCSURF 0x7219C 2390 #define DSPCTILEOFF 0x721A4 2391 #define DSPCSURFLIVE 0x721AC 2392 2393 #define VGACNTRL 0x71400 2394 # define VGA_DISP_DISABLE (1 << 31) 2395 # define VGA_2X_MODE (1 << 30) 2396 # define VGA_PIPE_B_SELECT (1 << 29) 2397 2398 /* Various masks for reserved bits, etc. */ 2399 #define I830_FWATER1_MASK (~((1<<11)|(1<<10)|(1<<9)| \ 2400 (1<<8)|(1<<26)|(1<<25)|(1<<24)|(1<<5)|(1<<4)|(1<<3)| \ 2401 (1<<2)|(1<<1)|1|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16))) 2402 #define I830_FWATER2_MASK ~(0) 2403 2404 #define DV0A_RESERVED ((1<<26)|(1<<25)|(1<<24)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<16)|(1<<5)|(1<<1)|1) 2405 #define DV0B_RESERVED ((1<<27)|(1<<26)|(1<<25)|(1<<24)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<16)|(1<<5)|(1<<1)|1) 2406 #define VGA0_N_DIVISOR_MASK ((1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)) 2407 #define VGA0_M1_DIVISOR_MASK ((1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8)) 2408 #define VGA0_M2_DIVISOR_MASK ((1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1) 2409 #define VGA0_M1M2N_RESERVED ~(VGA0_N_DIVISOR_MASK|VGA0_M1_DIVISOR_MASK|VGA0_M2_DIVISOR_MASK) 2410 #define VGA0_POSTDIV_MASK ((1<<7)|(1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1) 2411 #define VGA1_POSTDIV_MASK ((1<<15)|(1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8)) 2412 #define VGA_POSTDIV_RESERVED ~(VGA0_POSTDIV_MASK|VGA1_POSTDIV_MASK|(1<<7)|(1<<15)) 2413 #define DPLLA_POSTDIV_MASK ((1<<23)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)) 2414 #define DPLLA_RESERVED ((1<<27)|(1<<26)|(1<<25)|(1<<24)|(1<<22)|(1<<15)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8)|(1<<7)|(1<<6)|(1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1) 2415 #define ADPA_RESERVED ((1<<2)|(1<<1)|1|(1<<9)|(1<<8)|(1<<7)|(1<<6)|(1<<5)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(1<<26)|(1<<25)|(1<<24)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)) 2416 #define SUPER_WORD 32 2417 #define BURST_A_MASK ((1<<11)|(1<<10)|(1<<9)|(1<<8)) 2418 #define BURST_B_MASK ((1<<26)|(1<<25)|(1<<24)) 2419 #define WATER_A_MASK ((1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1) 2420 #define WATER_B_MASK ((1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)) 2421 #define WATER_RESERVED ((1<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(1<<23)|(1<<22)|(1<<21)|(1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<7)|(1<<6)) 2422 #define PIPEACONF_RESERVED ((1<<29)|(1<<28)|(1<<27)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)|0xffff) 2423 #define PIPEBCONF_RESERVED ((1<<30)|(1<<29)|(1<<28)|(1<<27)|(1<<26)|(1<<25)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)|0xffff) 2424 #define DSPACNTR_RESERVED ((1<<23)|(1<<19)|(1<<17)|(1<<16)|0xffff) 2425 #define DSPBCNTR_RESERVED ((1<<23)|(1<<19)|(1<<17)|(1<<16)|0x7ffe) 2426 2427 #define I830_GMCH_CTRL 0x52 2428 2429 #define I830_GMCH_ENABLED 0x4 2430 #define I830_GMCH_MEM_MASK 0x1 2431 #define I830_GMCH_MEM_64M 0x1 2432 #define I830_GMCH_MEM_128M 0 2433 2434 #define I830_GMCH_GMS_MASK 0x70 2435 #define I830_GMCH_GMS_DISABLED 0x00 2436 #define I830_GMCH_GMS_LOCAL 0x10 2437 #define I830_GMCH_GMS_STOLEN_512 0x20 2438 #define I830_GMCH_GMS_STOLEN_1024 0x30 2439 #define I830_GMCH_GMS_STOLEN_8192 0x40 2440 2441 #define I830_RDRAM_CHANNEL_TYPE 0x03010 2442 #define I830_RDRAM_ND(x) (((x) & 0x20) >> 5) 2443 #define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3) 2444 2445 #define I855_GMCH_GMS_MASK (0xF << 4) 2446 #define I855_GMCH_GMS_DISABLED 0x00 2447 #define I855_GMCH_GMS_STOLEN_1M (0x1 << 4) 2448 #define I855_GMCH_GMS_STOLEN_4M (0x2 << 4) 2449 #define I855_GMCH_GMS_STOLEN_8M (0x3 << 4) 2450 #define I855_GMCH_GMS_STOLEN_16M (0x4 << 4) 2451 #define I855_GMCH_GMS_STOLEN_32M (0x5 << 4) 2452 #define I915G_GMCH_GMS_STOLEN_48M (0x6 << 4) 2453 #define I915G_GMCH_GMS_STOLEN_64M (0x7 << 4) 2454 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) 2455 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) 2456 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) 2457 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) 2458 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) 2459 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) 2460 2461 2462 #define I85X_CAPID 0x44 2463 #define I85X_VARIANT_MASK 0x7 2464 #define I85X_VARIANT_SHIFT 5 2465 #define I855_GME 0x0 2466 #define I855_GM 0x4 2467 #define I852_GME 0x2 2468 #define I852_GM 0x5 2469 2470 #define I915_GCFGC 0xf0 2471 #define I915_LOW_FREQUENCY_ENABLE (1 << 7) 2472 #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 2473 #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4) 2474 #define I915_DISPLAY_CLOCK_MASK (7 << 4) 2475 2476 #define I855_HPLLCC 0xc0 2477 #define I855_CLOCK_CONTROL_MASK (3 << 0) 2478 #define I855_CLOCK_133_200 (0 << 0) 2479 #define I855_CLOCK_100_200 (1 << 0) 2480 #define I855_CLOCK_100_133 (2 << 0) 2481 #define I855_CLOCK_166_250 (3 << 0) 2482 2483 /* BLT commands */ 2484 #define COLOR_BLT_CMD ((2<<29)|(0x40<<22)|(0x3)) 2485 #define COLOR_BLT_WRITE_ALPHA (1<<21) 2486 #define COLOR_BLT_WRITE_RGB (1<<20) 2487 2488 #define XY_COLOR_BLT_CMD_NOLEN ((2<<29)|(0x50<<22)) 2489 #define XY_COLOR_BLT_WRITE_ALPHA (1<<21) 2490 #define XY_COLOR_BLT_WRITE_RGB (1<<20) 2491 #define XY_COLOR_BLT_TILED (1<<11) 2492 2493 #define XY_SETUP_CLIP_BLT_CMD ((2<<29)|(3<<22)|1) 2494 2495 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)) 2496 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 2497 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 2498 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) 2499 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) 2500 2501 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|0x4) 2502 #define SRC_COPY_BLT_WRITE_ALPHA (1<<21) 2503 #define SRC_COPY_BLT_WRITE_RGB (1<<20) 2504 2505 #define XY_PAT_BLT_IMMEDIATE ((2<<29)|(0x72<<22)) 2506 2507 #define XY_MONO_PAT_BLT_CMD ((0x2<<29)|(0x52<<22)|0x7) 2508 #define XY_MONO_PAT_VERT_SEED ((1<<10)|(1<<9)|(1<<8)) 2509 #define XY_MONO_PAT_HORT_SEED ((1<<14)|(1<<13)|(1<<12)) 2510 #define XY_MONO_PAT_BLT_WRITE_ALPHA (1<<21) 2511 #define XY_MONO_PAT_BLT_WRITE_RGB (1<<20) 2512 2513 #define XY_MONO_SRC_BLT_CMD ((0x2<<29)|(0x54<<22)|(0x6)) 2514 #define XY_MONO_SRC_BLT_WRITE_ALPHA (1<<21) 2515 #define XY_MONO_SRC_BLT_WRITE_RGB (1<<20) 2516 2517 #define XY_FAST_COPY_BLT ((2<<29)|(0x42<<22)|0x8) 2518 /* dword 0 */ 2519 #define XY_FAST_COPY_SRC_TILING_LINEAR (0 << 20) 2520 #define XY_FAST_COPY_SRC_TILING_X (1 << 20) 2521 #define XY_FAST_COPY_SRC_TILING_Yb_Yf (2 << 20) 2522 #define XY_FAST_COPY_SRC_TILING_Ys (3 << 20) 2523 #define XY_FAST_COPY_SRC_HORIZONTAL_ALIGNMENT(n) (n << 17) 2524 #define XY_FAST_COPY_SRC_VERTICAL_ALIGNMENT(n) (n << 15) 2525 #define XY_FAST_COPY_DST_TILING_X (1 << 13) 2526 #define XY_FAST_COPY_DST_TILING_Yb_Yf (2 << 13) 2527 #define XY_FAST_COPY_DST_TILING_Ys (3 << 13) 2528 #define XY_FAST_COPY_DST_HORIZONTAL_ALIGNMENT(n) (n << 10) 2529 #define XY_FAST_COPY_DST_VERTICAL_ALIGNMENT(n) (n << 8) 2530 /* dword 1 */ 2531 #define XY_FAST_COPY_SRC_TILING_Yf (1 << 31) 2532 #define XY_FAST_COPY_DST_TILING_Yf (1 << 30) 2533 #define XY_FAST_COPY_COLOR_DEPTH_8 (0 << 24) 2534 #define XY_FAST_COPY_COLOR_DEPTH_16 (1 << 24) 2535 #define XY_FAST_COPY_COLOR_DEPTH_32 (3 << 24) 2536 #define XY_FAST_COPY_COLOR_DEPTH_64 (4 << 24) 2537 #define XY_FAST_COPY_COLOR_DEPTH_128 (5 << 24) 2538 2539 #define MI_STORE_DWORD_IMM ((0x20<<23)|2) 2540 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 2541 2542 #define MI_SET_CONTEXT (0x18<<23) 2543 #define CTXT_NO_RESTORE (1) 2544 #define CTXT_PALETTE_SAVE_DISABLE (1<<3) 2545 #define CTXT_PALETTE_RESTORE_DISABLE (1<<2) 2546 2547 /* Dword 0 */ 2548 #define MI_VERTEX_BUFFER (0x17<<23) 2549 #define MI_VERTEX_BUFFER_IDX(x) (x<<20) 2550 #define MI_VERTEX_BUFFER_PITCH(x) (x<<13) 2551 #define MI_VERTEX_BUFFER_WIDTH(x) (x<<6) 2552 /* Dword 1 */ 2553 #define MI_VERTEX_BUFFER_DISABLE (1) 2554 2555 /* Overlay Flip */ 2556 #define MI_OVERLAY_FLIP (0x11<<23) 2557 #define MI_OVERLAY_FLIP_CONTINUE (0<<21) 2558 #define MI_OVERLAY_FLIP_ON (1<<21) 2559 #define MI_OVERLAY_FLIP_OFF (2<<21) 2560 2561 /* Wait for Events */ 2562 #define MI_WAIT_FOR_EVENT (0x03<<23) 2563 #define MI_WAIT_FOR_PIPEB_SVBLANK (1<<18) 2564 #define MI_WAIT_FOR_PIPEA_SVBLANK (1<<17) 2565 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 2566 #define MI_WAIT_FOR_PIPEB_VBLANK (1<<7) 2567 #define MI_WAIT_FOR_PIPEA_VBLANK (1<<3) 2568 #define MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW (1<<5) 2569 #define MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW (1<<1) 2570 2571 #define MI_LOAD_SCAN_LINES_INCL (0x12<<23) 2572 #define MI_LOAD_REGISTER_IMM ((0x22 << 23) | 1) 2573 2574 /* Flush */ 2575 #define MI_FLUSH (0x04<<23) 2576 #define MI_WRITE_DIRTY_STATE (1<<4) 2577 #define MI_END_SCENE (1<<3) 2578 #define MI_GLOBAL_SNAPSHOT_COUNT_RESET (1<<3) 2579 #define MI_INHIBIT_RENDER_CACHE_FLUSH (1<<2) 2580 #define MI_STATE_INSTRUCTION_CACHE_FLUSH (1<<1) 2581 #define MI_INVALIDATE_MAP_CACHE (1<<0) 2582 /* broadwater flush bits */ 2583 #define BRW_MI_GLOBAL_SNAPSHOT_RESET (1 << 3) 2584 2585 /* Noop */ 2586 #define MI_NOOP 0x00 2587 #define MI_NOOP_WRITE_ID (1<<22) 2588 #define MI_NOOP_ID_MASK (1<<22 - 1) 2589 2590 #define STATE3D_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x01<<16)) 2591 2592 /* Batch */ 2593 #define MI_BATCH_BUFFER ((0x30 << 23) | 1) 2594 #define MI_BATCH_BUFFER_START (0x31 << 23) 2595 #define MI_BATCH_BUFFER_END (0xA << 23) 2596 #define MI_BATCH_NON_SECURE (1) 2597 #define MI_BATCH_NON_SECURE_I965 (1 << 8) 2598 #define MI_BATCH_NON_SECURE_HSW (1<<13) /* Additional bit for RCS */ 2599 2600 #define MAX_DISPLAY_PIPES 2 2601 2602 typedef enum { 2603 CrtIndex = 0, 2604 TvIndex, 2605 DfpIndex, 2606 LfpIndex, 2607 Crt2Index, 2608 Tv2Index, 2609 Dfp2Index, 2610 Lfp2Index, 2611 NumDisplayTypes 2612 } DisplayType; 2613 2614 /* What's connected to the pipes (as reported by the BIOS) */ 2615 #define PIPE_ACTIVE_MASK 0xff 2616 #define PIPE_CRT_ACTIVE (1 << CrtIndex) 2617 #define PIPE_TV_ACTIVE (1 << TvIndex) 2618 #define PIPE_DFP_ACTIVE (1 << DfpIndex) 2619 #define PIPE_LCD_ACTIVE (1 << LfpIndex) 2620 #define PIPE_CRT2_ACTIVE (1 << Crt2Index) 2621 #define PIPE_TV2_ACTIVE (1 << Tv2Index) 2622 #define PIPE_DFP2_ACTIVE (1 << Dfp2Index) 2623 #define PIPE_LCD2_ACTIVE (1 << Lfp2Index) 2624 2625 #define PIPE_SIZED_DISP_MASK (PIPE_DFP_ACTIVE | \ 2626 PIPE_LCD_ACTIVE | \ 2627 PIPE_DFP2_ACTIVE) 2628 2629 #define PIPE_A_SHIFT 0 2630 #define PIPE_B_SHIFT 8 2631 #define PIPE_SHIFT(n) ((n) == 0 ? \ 2632 PIPE_A_SHIFT : PIPE_B_SHIFT) 2633 2634 /* 2635 * Some BIOS scratch area registers. The 845 (and 830?) store the amount 2636 * of video memory available to the BIOS in SWF1. 2637 */ 2638 2639 #define SWF0 0x71410 2640 #define SWF1 0x71414 2641 #define SWF2 0x71418 2642 #define SWF3 0x7141c 2643 #define SWF4 0x71420 2644 #define SWF5 0x71424 2645 #define SWF6 0x71428 2646 2647 /* 2648 * 855 scratch registers. 2649 */ 2650 #define SWF00 0x70410 2651 #define SWF01 0x70414 2652 #define SWF02 0x70418 2653 #define SWF03 0x7041c 2654 #define SWF04 0x70420 2655 #define SWF05 0x70424 2656 #define SWF06 0x70428 2657 2658 #define SWF10 SWF0 2659 #define SWF11 SWF1 2660 #define SWF12 SWF2 2661 #define SWF13 SWF3 2662 #define SWF14 SWF4 2663 #define SWF15 SWF5 2664 #define SWF16 SWF6 2665 2666 #define SWF30 0x72414 2667 #define SWF31 0x72418 2668 #define SWF32 0x7241c 2669 2670 /* 2671 * Overlay registers. These are overlay registers accessed via MMIO. 2672 * Those loaded via the overlay register page are defined in i830_video.c. 2673 */ 2674 #define OVADD 0x30000 2675 2676 #define DOVSTA 0x30008 2677 #define OC_BUF (0x3<<20) 2678 2679 #define OGAMC5 0x30010 2680 #define OGAMC4 0x30014 2681 #define OGAMC3 0x30018 2682 #define OGAMC2 0x3001c 2683 #define OGAMC1 0x30020 2684 #define OGAMC0 0x30024 2685 2686 2687 /* 2688 * Palette registers 2689 */ 2690 #define PALETTE_A 0x0a000 2691 #define PALETTE_B 0x0a800 2692 2693 /* Framebuffer compression */ 2694 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 2695 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 2696 #define FBC_CONTROL 0x03208 2697 #define FBC_CTL_EN (1<<31) 2698 #define FBC_CTL_PERIODIC (1<<30) 2699 #define FBC_CTL_INTERVAL_SHIFT (16) 2700 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 2701 #define FBC_CTL_STRIDE_SHIFT (5) 2702 #define FBC_CTL_FENCENO (1<<0) 2703 #define FBC_COMMAND 0x0320c 2704 #define FBC_CMD_COMPRESS (1<<0) 2705 #define FBC_STATUS 0x03210 2706 #define FBC_STAT_COMPRESSING (1<<31) 2707 #define FBC_STAT_COMPRESSED (1<<30) 2708 #define FBC_STAT_MODIFIED (1<<29) 2709 #define FBC_STAT_CURRENT_LINE (1<<0) 2710 #define FBC_CONTROL2 0x03214 2711 #define FBC_CTL_FENCE_DBL (0<<4) 2712 #define FBC_CTL_IDLE_IMM (0<<2) 2713 #define FBC_CTL_IDLE_FULL (1<<2) 2714 #define FBC_CTL_IDLE_LINE (2<<2) 2715 #define FBC_CTL_IDLE_DEBUG (3<<2) 2716 #define FBC_CTL_CPU_FENCE (1<<1) 2717 #define FBC_CTL_PLANEA (0<<0) 2718 #define FBC_CTL_PLANEB (1<<0) 2719 #define FBC_FENCE_OFF 0x0321b 2720 #define FBC_MOD_NUM 0x03220 2721 #define FBC_TAG_DEBUG 0x03300 2722 2723 #define FBC_LL_SIZE (1536) 2724 #define FBC_LL_PAD (32) 2725 2726 /* Framebuffer compression version 2 */ 2727 #define DPFC_CB_BASE 0x3200 2728 #define DPFC_CONTROL 0x3208 2729 #define DPFC_CTL_EN (1<<31) 2730 #define DPFC_CTL_PLANEA (0<<30) 2731 #define DPFC_CTL_PLANEB (1<<30) 2732 #define DPFC_CTL_FENCE_EN (1<<29) 2733 #define DPFC_CTL_LIMIT_1X (0<<6) 2734 #define DPFC_CTL_LIMIT_2X (1<<6) 2735 #define DPFC_CTL_LIMIT_4X (2<<6) 2736 #define DPFC_RECOMP_CTL 0x320c 2737 #define DPFC_RECOMP_STALL_EN (1<<27) 2738 #define DPFC_RECOMP_STALL_WM_SHIFT (16) 2739 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 2740 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 2741 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 2742 #define DPFC_STATUS 0x3210 2743 #define DPFC_INVAL_SEG_SHIFT (16) 2744 #define DPFC_INVAL_SEG_MASK (0x07ff0000) 2745 #define DPFC_COMP_SEG_SHIFT (0) 2746 #define DPFC_COMP_SEG_MASK (0x000003ff) 2747 #define DPFC_STATUS2 0x3214 2748 #define DPFC_FENCE_YOFF 0x3218 2749 2750 #define PEG_BAND_GAP_DATA 0x14d68 2751 2752 #define MCHBAR_RENDER_STANDBY 0x111B8 2753 #define RENDER_STANDBY_ENABLE (1 << 30) 2754 2755 2756 /* Ironlake */ 2757 2758 /* warmup time in us */ 2759 #define WARMUP_PCH_REF_CLK_SSC_MOD 1 2760 #define WARMUP_PCH_FDI_RECEIVER_PLL 25 2761 #define WARMUP_PCH_DPLL 50 2762 #define WARMUP_CPU_DP_PLL 20 2763 #define WARMUP_CPU_FDI_TRANSMITTER_PLL 10 2764 #define WARMUP_DMI_LATENCY 20 2765 #define FDI_TRAIN_PATTERN_1_TIME 0.5 2766 #define FDI_TRAIN_PATTERN_2_TIME 1.5 2767 #define FDI_ONE_IDLE_PATTERN_TIME 31 2768 2769 #define CPU_VGACNTRL 0x41000 2770 2771 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 2772 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 2773 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) 2774 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) 2775 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) 2776 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) 2777 #define DIGITAL_PORTA_NO_DETECT (0 << 0) 2778 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) 2779 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) 2780 2781 /* refresh rate hardware control */ 2782 #define RR_HW_CTL 0x45300 2783 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 2784 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 2785 2786 #define FDI_PLL_BIOS_0 0x46000 2787 #define FDI_PLL_BIOS_1 0x46004 2788 #define FDI_PLL_BIOS_2 0x46008 2789 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c 2790 #define DISPLAY_PORT_PLL_BIOS_1 0x46010 2791 #define DISPLAY_PORT_PLL_BIOS_2 0x46014 2792 2793 #define FDI_PLL_FREQ_CTL 0x46030 2794 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 2795 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 2796 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 2797 2798 #define PIPEA_DATA_M1 0x60030 2799 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 2800 #define TU_SIZE_MASK 0x7e000000 2801 #define PIPEA_DATA_M1_OFFSET 0 2802 #define PIPEA_DATA_N1 0x60034 2803 #define PIPEA_DATA_N1_OFFSET 0 2804 2805 #define PIPEA_DATA_M2 0x60038 2806 #define PIPEA_DATA_M2_OFFSET 0 2807 #define PIPEA_DATA_N2 0x6003c 2808 #define PIPEA_DATA_N2_OFFSET 0 2809 2810 #define PIPEA_LINK_M1 0x60040 2811 #define PIPEA_LINK_M1_OFFSET 0 2812 #define PIPEA_LINK_N1 0x60044 2813 #define PIPEA_LINK_N1_OFFSET 0 2814 2815 #define PIPEA_LINK_M2 0x60048 2816 #define PIPEA_LINK_M2_OFFSET 0 2817 #define PIPEA_LINK_N2 0x6004c 2818 #define PIPEA_LINK_N2_OFFSET 0 2819 2820 /* PIPEB timing regs are same start from 0x61000 */ 2821 2822 #define PIPEB_DATA_M1 0x61030 2823 #define PIPEB_DATA_N1 0x61034 2824 2825 #define PIPEB_DATA_M2 0x61038 2826 #define PIPEB_DATA_N2 0x6103c 2827 2828 #define PIPEB_LINK_M1 0x61040 2829 #define PIPEB_LINK_N1 0x61044 2830 2831 #define PIPEB_LINK_M2 0x61048 2832 #define PIPEB_LINK_N2 0x6104c 2833 2834 /* PIPEC timing regs */ 2835 2836 #define PIPEC_DATA_M1 0x62030 2837 #define PIPEC_DATA_N1 0x62034 2838 2839 #define PIPEC_DATA_M2 0x62038 2840 #define PIPEC_DATA_N2 0x6203c 2841 2842 #define PIPEC_LINK_M1 0x62040 2843 #define PIPEC_LINK_N1 0x62044 2844 2845 #define PIPEC_LINK_M2 0x62048 2846 #define PIPEC_LINK_N2 0x6204c 2847 2848 #define PIPEEDP_DATA_M1 0x6F030 2849 #define PIPEEDP_DATA_N1 0x6F034 2850 2851 #define PIPEEDP_LINK_M1 0x6F040 2852 #define PIPEEDP_LINK_N1 0x6F044 2853 2854 /* PIPECONF for pipe A/B addr is same */ 2855 2856 /* cusor A is only connected to pipe A, 2857 cursor B is connected to pipe B. Otherwise no change. */ 2858 2859 /* Plane A/B, DSPACNTR/DSPBCNTR addr not changed */ 2860 2861 /* CPU panel fitter */ 2862 #define PFA_CTL_1 0x68080 2863 #define PFB_CTL_1 0x68880 2864 #define PFC_CTL_1 0x69080 2865 #define PF_ENABLE (1<<31) 2866 #define PFA_CTL_2 0x68084 2867 #define PFB_CTL_2 0x68884 2868 #define PFC_CTL_2 0x69084 2869 #define PFA_CTL_3 0x68088 2870 #define PFB_CTL_3 0x68888 2871 #define PFC_CTL_3 0x69088 2872 #define PFA_CTL_4 0x68090 2873 #define PFB_CTL_4 0x68890 2874 #define PFC_CTL_4 0x69090 2875 2876 #define PFA_WIN_POS 0x68070 2877 #define PFB_WIN_POS 0x68870 2878 #define PFC_WIN_POS 0x69070 2879 #define PFA_WIN_SIZE 0x68074 2880 #define PFB_WIN_SIZE 0x68874 2881 #define PFC_WIN_SIZE 0x69074 2882 2883 /* legacy palette */ 2884 #define LGC_PALETTE_A 0x4a000 2885 #define LGC_PALETTE_B 0x4a800 2886 2887 /* interrupts */ 2888 #define DE_MASTER_IRQ_CONTROL (1 << 31) 2889 #define DE_SPRITEB_FLIP_DONE (1 << 29) 2890 #define DE_SPRITEA_FLIP_DONE (1 << 28) 2891 #define DE_PLANEB_FLIP_DONE (1 << 27) 2892 #define DE_PLANEA_FLIP_DONE (1 << 26) 2893 #define DE_PCU_EVENT (1 << 25) 2894 #define DE_GTT_FAULT (1 << 24) 2895 #define DE_POISON (1 << 23) 2896 #define DE_PERFORM_COUNTER (1 << 22) 2897 #define DE_PCH_EVENT (1 << 21) 2898 #define DE_AUX_CHANNEL_A (1 << 20) 2899 #define DE_DP_A_HOTPLUG (1 << 19) 2900 #define DE_GSE (1 << 18) 2901 #define DE_PIPEB_VBLANK (1 << 15) 2902 #define DE_PIPEB_EVEN_FIELD (1 << 14) 2903 #define DE_PIPEB_ODD_FIELD (1 << 13) 2904 #define DE_PIPEB_LINE_COMPARE (1 << 12) 2905 #define DE_PIPEB_VSYNC (1 << 11) 2906 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 2907 #define DE_PIPEA_VBLANK (1 << 7) 2908 #define DE_PIPEA_EVEN_FIELD (1 << 6) 2909 #define DE_PIPEA_ODD_FIELD (1 << 5) 2910 #define DE_PIPEA_LINE_COMPARE (1 << 4) 2911 #define DE_PIPEA_VSYNC (1 << 3) 2912 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 2913 2914 #define DEISR 0x44000 2915 #define DEIMR 0x44004 2916 #define DEIIR 0x44008 2917 #define DEIER 0x4400c 2918 2919 #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + 0x10 * (pipe)) 2920 #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + 0x10 * (pipe)) 2921 #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + 0x10 * (pipe)) 2922 #define GEN8_DE_PIPE_IER(pipe) (0x4440c + 0x10 * (pipe)) 2923 2924 /* GT interrupt */ 2925 #define GT_SYNC_STATUS (1 << 2) 2926 #define GT_USER_INTERRUPT (1 << 0) 2927 2928 #define GTISR 0x44010 2929 #define GTIMR 0x44014 2930 #define GTIIR 0x44018 2931 #define GTIER 0x4401c 2932 2933 /* PCH */ 2934 2935 /* south display engine interrupt */ 2936 #define SDE_CRT_HOTPLUG (1 << 11) 2937 #define SDE_PORTD_HOTPLUG (1 << 10) 2938 #define SDE_PORTC_HOTPLUG (1 << 9) 2939 #define SDE_PORTB_HOTPLUG (1 << 8) 2940 #define SDE_SDVOB_HOTPLUG (1 << 6) 2941 2942 #define SDEISR 0xc4000 2943 #define SDEIMR 0xc4004 2944 #define SDEIIR 0xc4008 2945 #define SDEIER 0xc400c 2946 2947 /* digital port hotplug */ 2948 #define PCH_PORT_HOTPLUG 0xc4030 2949 #define PORTD_HOTPLUG_ENABLE (1 << 20) 2950 #define PORTD_PULSE_DURATION_2ms (0) 2951 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) 2952 #define PORTD_PULSE_DURATION_6ms (2 << 18) 2953 #define PORTD_PULSE_DURATION_100ms (3 << 18) 2954 #define PORTD_HOTPLUG_NO_DETECT (0) 2955 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 2956 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17) 2957 #define PORTC_HOTPLUG_ENABLE (1 << 12) 2958 #define PORTC_PULSE_DURATION_2ms (0) 2959 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) 2960 #define PORTC_PULSE_DURATION_6ms (2 << 10) 2961 #define PORTC_PULSE_DURATION_100ms (3 << 10) 2962 #define PORTC_HOTPLUG_NO_DETECT (0) 2963 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 2964 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9) 2965 #define PORTB_HOTPLUG_ENABLE (1 << 4) 2966 #define PORTB_PULSE_DURATION_2ms (0) 2967 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) 2968 #define PORTB_PULSE_DURATION_6ms (2 << 2) 2969 #define PORTB_PULSE_DURATION_100ms (3 << 2) 2970 #define PORTB_HOTPLUG_NO_DETECT (0) 2971 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 2972 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1) 2973 2974 #define PCH_GPIOA 0xc5010 2975 #define PCH_GPIOB 0xc5014 2976 #define PCH_GPIOC 0xc5018 2977 #define PCH_GPIOD 0xc501c 2978 #define PCH_GPIOE 0xc5020 2979 #define PCH_GPIOF 0xc5024 2980 #define PCH_GMBUS0 0xc5100 2981 #define PCH_GMBUS1 0xc5104 2982 #define PCH_GMBUS2 0xc5108 2983 #define PCH_GMBUS3 0xc510c 2984 #define PCH_GMBUS4 0xc5110 2985 #define PCH_GMBUS5 0xc5120 2986 2987 #define PCH_DPLL_A 0xc6014 2988 #define PCH_DPLL_B 0xc6018 2989 2990 #define PCH_FPA0 0xc6040 2991 #define PCH_FPA1 0xc6044 2992 #define PCH_FPB0 0xc6048 2993 #define PCH_FPB1 0xc604c 2994 2995 #define PCH_DPLL_TEST 0xc606c 2996 2997 #define PCH_DREF_CONTROL 0xC6200 2998 #define DREF_CONTROL_MASK 0x7fc3 2999 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 3000 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 3001 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 3002 #define DREF_SSC_SOURCE_DISABLE (0<<11) 3003 #define DREF_SSC_SOURCE_ENABLE (2<<11) 3004 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 3005 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 3006 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 3007 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 3008 #define DREF_SSC4_DOWNSPREAD (0<<6) 3009 #define DREF_SSC4_CENTERSPREAD (1<<6) 3010 #define DREF_SSC1_DISABLE (0<<1) 3011 #define DREF_SSC1_ENABLE (1<<1) 3012 #define DREF_SSC4_DISABLE (0) 3013 #define DREF_SSC4_ENABLE (1) 3014 3015 #define PCH_RAWCLK_FREQ 0xc6204 3016 #define FDL_TP1_TIMER_SHIFT 12 3017 #define FDL_TP1_TIMER_MASK (3<<12) 3018 #define FDL_TP2_TIMER_SHIFT 10 3019 #define FDL_TP2_TIMER_MASK (3<<10) 3020 #define RAWCLK_FREQ_MASK 0x3ff 3021 3022 #define PCH_DPLL_TMR_CFG 0xc6208 3023 3024 #define PCH_SSC4_PARMS 0xc6210 3025 #define PCH_SSC4_AUX_PARMS 0xc6214 3026 3027 /* CPT */ 3028 #define PCH_DPLL_ANALOG_CTL 0xc6300 3029 3030 #define PCH_DPLL_SEL 0xc7000 3031 #define TRANSA_DPLL_ENABLE (1<<3) 3032 #define TRANSA_DPLLA_SEL (0) 3033 #define TRANSA_DPLLB_SEL (1<<0) 3034 #define TRANSB_DPLL_ENABLE (1<<7) 3035 #define TRANSB_DPLLA_SEL (0<<4) 3036 #define TRANSB_DPLLB_SEL (1<<4) 3037 #define TRANSC_DPLL_ENABLE (1<<11) 3038 #define TRANSC_DPLLA_SEL (0<<8) 3039 #define TRANSC_DPLLB_SEL (1<<8) 3040 3041 /* transcoder */ 3042 3043 #define TRANS_HTOTAL_A 0xe0000 3044 #define TRANS_HTOTAL_SHIFT 16 3045 #define TRANS_HACTIVE_SHIFT 0 3046 #define TRANS_HBLANK_A 0xe0004 3047 #define TRANS_HBLANK_END_SHIFT 16 3048 #define TRANS_HBLANK_START_SHIFT 0 3049 #define TRANS_HSYNC_A 0xe0008 3050 #define TRANS_HSYNC_END_SHIFT 16 3051 #define TRANS_HSYNC_START_SHIFT 0 3052 #define TRANS_VTOTAL_A 0xe000c 3053 #define TRANS_VTOTAL_SHIFT 16 3054 #define TRANS_VACTIVE_SHIFT 0 3055 #define TRANS_VBLANK_A 0xe0010 3056 #define TRANS_VBLANK_END_SHIFT 16 3057 #define TRANS_VBLANK_START_SHIFT 0 3058 #define TRANS_VSYNC_A 0xe0014 3059 #define TRANS_VSYNC_END_SHIFT 16 3060 #define TRANS_VSYNC_START_SHIFT 0 3061 #define TRANS_VSYNCSHIFT_A 0xe0028 3062 3063 #define TRANSA_DATA_M1 0xe0030 3064 #define TRANSA_DATA_N1 0xe0034 3065 #define TRANSA_DATA_M2 0xe0038 3066 #define TRANSA_DATA_N2 0xe003c 3067 #define TRANSA_DP_LINK_M1 0xe0040 3068 #define TRANSA_DP_LINK_N1 0xe0044 3069 #define TRANSA_DP_LINK_M2 0xe0048 3070 #define TRANSA_DP_LINK_N2 0xe004c 3071 3072 #define TRANS_HTOTAL_B 0xe1000 3073 #define TRANS_HBLANK_B 0xe1004 3074 #define TRANS_HSYNC_B 0xe1008 3075 #define TRANS_VTOTAL_B 0xe100c 3076 #define TRANS_VBLANK_B 0xe1010 3077 #define TRANS_VSYNC_B 0xe1014 3078 #define TRANS_VSYNCSHIFT_B 0xe1028 3079 3080 #define TRANSB_DATA_M1 0xe1030 3081 #define TRANSB_DATA_N1 0xe1034 3082 #define TRANSB_DATA_M2 0xe1038 3083 #define TRANSB_DATA_N2 0xe103c 3084 #define TRANSB_DP_LINK_M1 0xe1040 3085 #define TRANSB_DP_LINK_N1 0xe1044 3086 #define TRANSB_DP_LINK_M2 0xe1048 3087 #define TRANSB_DP_LINK_N2 0xe104c 3088 3089 #define TRANS_HTOTAL_C 0xe2000 3090 #define TRANS_HBLANK_C 0xe2004 3091 #define TRANS_HSYNC_C 0xe2008 3092 #define TRANS_VTOTAL_C 0xe200c 3093 #define TRANS_VBLANK_C 0xe2010 3094 #define TRANS_VSYNC_C 0xe2014 3095 #define TRANS_VSYNCSHIFT_C 0xe2028 3096 3097 #define TRANSC_DATA_M1 0xe2030 3098 #define TRANSC_DATA_N1 0xe2034 3099 #define TRANSC_DATA_M2 0xe2038 3100 #define TRANSC_DATA_N2 0xe203c 3101 #define TRANSC_DP_LINK_M1 0xe2040 3102 #define TRANSC_DP_LINK_N1 0xe2044 3103 #define TRANSC_DP_LINK_M2 0xe2048 3104 #define TRANSC_DP_LINK_N2 0xe204c 3105 3106 #define DP_BUFTRANS(x) (0xe4f00 + 4 * (x)) 3107 3108 #define TRANSACONF 0xf0008 3109 #define TRANSBCONF 0xf1008 3110 #define TRANSCCONF 0xf2008 3111 #define TRANS_DISABLE (0<<31) 3112 #define TRANS_ENABLE (1<<31) 3113 #define TRANS_STATE_MASK (1<<30) 3114 #define TRANS_STATE_DISABLE (0<<30) 3115 #define TRANS_STATE_ENABLE (1<<30) 3116 #define TRANS_FSYNC_DELAY_HB1 (0<<27) 3117 #define TRANS_FSYNC_DELAY_HB2 (1<<27) 3118 #define TRANS_FSYNC_DELAY_HB3 (2<<27) 3119 #define TRANS_FSYNC_DELAY_HB4 (3<<27) 3120 #define TRANS_DP_AUDIO_ONLY (1<<26) 3121 #define TRANS_DP_VIDEO_AUDIO (0<<26) 3122 #define TRANS_PROGRESSIVE (0<<21) 3123 #define TRANS_8BPC (0<<5) 3124 #define TRANS_10BPC (1<<5) 3125 #define TRANS_6BPC (2<<5) 3126 #define TRANS_12BPC (3<<5) 3127 3128 #define FDI_RXA_CHICKEN 0xc200c 3129 #define FDI_RXB_CHICKEN 0xc2010 3130 #define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1) 3131 3132 /* CPU: FDI_TX */ 3133 #define FDI_TXA_CTL 0x60100 3134 #define FDI_TXB_CTL 0x61100 3135 #define FDI_TXC_CTL 0x62100 3136 #define FDI_TX_DISABLE (0<<31) 3137 #define FDI_TX_ENABLE (1<<31) 3138 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 3139 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 3140 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 3141 #define FDI_LINK_TRAIN_NONE (3<<28) 3142 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 3143 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 3144 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 3145 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 3146 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 3147 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 3148 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 3149 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 3150 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 3151 SNB has different settings. */ 3152 /* SNB A-stepping */ 3153 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 3154 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 3155 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 3156 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 3157 /* SNB B-stepping */ 3158 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 3159 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 3160 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 3161 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 3162 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) 3163 #define FDI_DP_PORT_WIDTH_X1 (0<<19) 3164 #define FDI_DP_PORT_WIDTH_X2 (1<<19) 3165 #define FDI_DP_PORT_WIDTH_X3 (2<<19) 3166 #define FDI_DP_PORT_WIDTH_X4 (3<<19) 3167 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 3168 /* Ironlake: hardwired to 1 */ 3169 #define FDI_TX_PLL_ENABLE (1<<14) 3170 /* both Tx and Rx */ 3171 #define FDI_SCRAMBLING_ENABLE (0<<7) 3172 #define FDI_SCRAMBLING_DISABLE (1<<7) 3173 3174 /* Additional cpu TX control regs, from ivb bspec */ 3175 #define DPAFE_BMFUNC 0x6c024 3176 #define DPAFE_DL_IREFCAL0 0x6c02c 3177 #define DPAFE_DL_IREFCAL1 0x6c030 3178 #define DPAFE_DP_IREFCAL 0x6c034 3179 3180 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 3181 #define FDI_RXA_CTL 0xf000c 3182 #define FDI_RXB_CTL 0xf100c 3183 #define FDI_RXC_CTL 0xf200c 3184 #define FDI_RX_ENABLE (1<<31) 3185 #define FDI_RX_DISABLE (0<<31) 3186 /* train, dp width same as FDI_TX */ 3187 #define FDI_DP_PORT_WIDTH_X8 (7<<19) 3188 #define FDI_8BPC (0<<16) 3189 #define FDI_10BPC (1<<16) 3190 #define FDI_6BPC (2<<16) 3191 #define FDI_12BPC (3<<16) 3192 #define FDI_LINK_REVERSE_OVERWRITE (1<<15) 3193 #define FDI_DMI_LINK_REVERSE_MASK (1<<14) 3194 #define FDI_RX_PLL_ENABLE (1<<13) 3195 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 3196 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 3197 #define FDI_FS_ERR_REPORT_ENABLE (1<<9) 3198 #define FDI_FE_ERR_REPORT_ENABLE (1<<8) 3199 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 3200 #define FDI_SEL_RAWCLK (0<<4) 3201 #define FDI_SEL_PCDCLK (1<<4) 3202 /* CPT */ 3203 #define FDI_AUTO_TRAINING (1<<10) 3204 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 3205 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) 3206 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) 3207 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 3208 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 3209 3210 #define FDI_RXA_MISC 0xf0010 3211 #define FDI_RXB_MISC 0xf1010 3212 #define FDI_RXC_MISC 0xf2010 3213 #define FDI_RXA_TUSIZE1 0xf0030 3214 #define FDI_RXA_TUSIZE2 0xf0038 3215 #define FDI_RXB_TUSIZE1 0xf1030 3216 #define FDI_RXB_TUSIZE2 0xf1038 3217 #define FDI_RXC_TUSIZE1 0xf2030 3218 #define FDI_RXC_TUSIZE2 0xf2038 3219 3220 /* FDI_RX interrupt register format */ 3221 #define FDI_RX_INTER_LANE_ALIGN (1<<10) 3222 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 3223 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 3224 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 3225 #define FDI_RX_FS_CODE_ERR (1<<6) 3226 #define FDI_RX_FE_CODE_ERR (1<<5) 3227 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 3228 #define FDI_RX_HDCP_LINK_FAIL (1<<3) 3229 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 3230 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 3231 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 3232 3233 #define FDI_RXA_IIR 0xf0014 3234 #define FDI_RXA_IMR 0xf0018 3235 #define FDI_RXB_IIR 0xf1014 3236 #define FDI_RXB_IMR 0xf1018 3237 3238 #define FDI_PLL_CTL_1 0xfe000 3239 #define FDI_PLL_CTL_2 0xfe004 3240 3241 /* CRT */ 3242 #define PCH_ADPA 0xe1100 3243 #define ADPA_TRANS_SELECT_MASK (1<<30) 3244 #define ADPA_TRANS_A_SELECT 0 3245 #define ADPA_TRANS_B_SELECT (1<<30) 3246 /* HPD is here */ 3247 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 3248 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 3249 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 3250 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 3251 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 3252 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 3253 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 3254 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 3255 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 3256 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 3257 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 3258 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 3259 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 3260 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 3261 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 3262 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 3263 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 3264 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 3265 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 3266 /* polarity control not changed */ 3267 3268 /* or SDVOB */ 3269 #define HDMIB 0xe1140 3270 #define PORT_ENABLE (1 << 31) 3271 #define TRANSCODER_A (0) 3272 #define TRANSCODER_B (1 << 30) 3273 #define COLOR_FORMAT_8bpc (0) 3274 #define COLOR_FORMAT_12bpc (3 << 26) 3275 #define SDVOB_HOTPLUG_ENABLE (1 << 23) 3276 #define SDVO_ENCODING (0) 3277 #define TMDS_ENCODING (2 << 10) 3278 #define NULL_PACKET_VSYNC_ENABLE (1 << 9) 3279 #define SDVOB_BORDER_ENABLE (1 << 7) 3280 #define AUDIO_ENABLE (1 << 6) 3281 #define VSYNC_ACTIVE_HIGH (1 << 4) 3282 #define HSYNC_ACTIVE_HIGH (1 << 3) 3283 #define PORT_DETECTED (1 << 2) 3284 3285 #define HDMIC 0xe1150 3286 #define HDMID 0xe1160 3287 #define PCH_LVDS 0xe1180 3288 3289 /* Since IVB, the old _CTL2 is now _CTL and the old _CTL is now _DATA. */ 3290 #define BLC_PWM_CPU_CTL2 0x48250 3291 #define BLC_PWM2_CPU_CTL2 0x48350 3292 #define PWM_ENABLE (1 << 31) 3293 #define PWM_PIPE_A (0 << 29) 3294 #define PWM_PIPE_B (1 << 29) 3295 #define BLC_PWM_CPU_CTL 0x48254 3296 #define BLC_PWM2_CPU_CTL 0x48354 3297 #define BLC_MISC_CTL 0x48360 3298 3299 #define UTIL_PIN_CTL 0x48400 3300 3301 #define BLC_PWM_PCH_CTL1 0xc8250 3302 #define PWM_PCH_ENABLE (1 << 31) 3303 #define PWM_POLARITY_ACTIVE_LOW (1 << 29) 3304 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29) 3305 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28) 3306 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28) 3307 3308 #define BLC_PWM_PCH_CTL2 0xc8254 3309 3310 #define PCH_PP_STATUS 0xc7200 3311 #define PCH_PP_CONTROL 0xc7204 3312 #define EDP_FORCE_VDD (1 << 3) 3313 #define EDP_BLC_ENABLE (1 << 2) 3314 #define PANEL_POWER_RESET (1 << 1) 3315 #define PANEL_POWER_OFF (0 << 0) 3316 #define PANEL_POWER_ON (1 << 0) 3317 #define PCH_PP_ON_DELAYS 0xc7208 3318 #define EDP_PANEL (1 << 30) 3319 #define PCH_PP_OFF_DELAYS 0xc720c 3320 #define PCH_PP_DIVISOR 0xc7210 3321 3322 #define AUD_CONFIG 0x62000 3323 #define AUD_DEBUG 0x62010 3324 #define AUD_VID_DID 0x62020 3325 #define AUD_RID 0x62024 3326 #define AUD_SUBN_CNT 0x62028 3327 #define AUD_FUNC_GRP 0x62040 3328 #define AUD_SUBN_CNT2 0x62044 3329 #define AUD_GRP_CAP 0x62048 3330 #define AUD_PWRST 0x6204c 3331 #define AUD_SUPPWR 0x62050 3332 #define AUD_SID 0x62054 3333 #define AUD_OUT_CWCAP 0x62070 3334 #define AUD_OUT_PCMSIZE 0x62074 3335 #define AUD_OUT_STR 0x62078 3336 #define AUD_OUT_DIG_CNVT 0x6207c 3337 #define AUD_OUT_CH_STR 0x62080 3338 #define AUD_OUT_STR_DESC 0x62084 3339 #define AUD_PINW_CAP 0x620a0 3340 #define AUD_PIN_CAP 0x620a4 3341 #define AUD_PINW_CONNLNG 0x620a8 3342 #define AUD_PINW_CONNLST 0x620ac 3343 #define AUD_PINW_CNTR 0x620b0 3344 #define AUD_PINW_UNSOLRESP 0x620b8 3345 #define AUD_CNTL_ST 0x620b4 3346 #define AUD_PINW_CONFIG 0x620bc 3347 #define AUD_HDMIW_STATUS 0x620d4 3348 #define AUD_HDMIW_HDMIEDID 0x6210c 3349 #define AUD_HDMIW_INFOFR 0x62118 3350 #define AUD_CONV_CHCNT 0x62120 3351 #define AUD_CTS_ENABLE 0x62128 3352 3353 #define VIDEO_DIP_CTL 0x61170 3354 #define VIDEO_DIP_DATA 0x61178 3355 3356 /* CPT */ 3357 #define TRANS_DP_CTL_A 0xe0300 3358 #define TRANS_DP_CTL_B 0xe1300 3359 #define TRANS_DP_CTL_C 0xe2300 3360 #define TRANS_DP_OUTPUT_ENABLE (1<<31) 3361 #define TRANS_DP_PORT_SEL_B (0<<29) 3362 #define TRANS_DP_PORT_SEL_C (1<<29) 3363 #define TRANS_DP_PORT_SEL_D (2<<29) 3364 #define TRANS_DP_PORT_SEL_MASK (3<<29) 3365 #define TRANS_DP_AUDIO_ONLY (1<<26) 3366 #define TRANS_DP_ENH_FRAMING (1<<18) 3367 #define TRANS_DP_8BPC (0<<9) 3368 #define TRANS_DP_10BPC (1<<9) 3369 #define TRANS_DP_6BPC (2<<9) 3370 #define TRANS_DP_12BPC (3<<9) 3371 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 3372 #define TRANS_DP_VSYNC_ACTIVE_LOW 0 3373 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 3374 #define TRANS_DP_HSYNC_ACTIVE_LOW 0 3375 3376 /* Debug regs */ 3377 #define GEN6_TD_CTL 0x7000 /* <= GEN5 was at 0x8000 */ 3378 #define GEN6_TD_CTL_FORCE_TD_BKPT (1<<4) 3379 3380 /* Port debugging 3381 */ 3382 3383 #define PORT_DBG 0x42308 3384 #define PORT_DBG_DRRS_HW_STATE_OFF (0<<30) 3385 #define PORT_DBG_DRRS_HW_STATE_LOW (1<<30) 3386 #define PORT_DBG_DRRS_HW_STATE_HIGH (2U<<30) 3387 3388 /* RC6 residence counters 3389 */ 3390 #define RC6_RESIDENCY_TIME 0x138108 3391 #define RC6p_RESIDENCY_TIME 0x13810C 3392 #define RC6pp_RESIDENCY_TIME 0x138110 3393 3394 #define GEN6_RPNSWREQ 0xA008 3395 #define GEN6_RC_VIDEO_FREQ 0xA00C 3396 #define GEN6_RC_CONTROL 0xA090 3397 #define GEN6_RP_DOWN_TIMEOUT 0xA010 3398 #define GEN6_RP_INTERRUPT_LIMITS 0xA014 3399 #define GEN6_RPSTAT1 0xA01C 3400 #define GEN6_RP_CONTROL 0xA024 3401 #define GEN6_RP_UP_THRESHOLD 0xA02C 3402 #define GEN6_RP_DOWN_THRESHOLD 0xA030 3403 #define GEN6_RP_CUR_UP_EI 0xA050 3404 #define GEN6_RP_CUR_UP 0xA054 3405 #define GEN6_RP_PREV_UP 0xA058 3406 #define GEN6_RP_CUR_DOWN_EI 0xA05C 3407 #define GEN6_RP_CUR_DOWN 0xA060 3408 #define GEN6_RP_PREV_DOWN 0xA064 3409 #define GEN6_RP_UP_EI 0xA068 3410 #define GEN6_RP_DOWN_EI 0xA06C 3411 #define GEN6_RP_IDLE_HYSTERSIS 0xA070 3412 #define GEN6_RC_STATE 0xA094 3413 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 3414 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C 3415 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 3416 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 3417 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC 3418 #define GEN6_RC_SLEEP 0xA0B0 3419 #define GEN6_RC1e_THRESHOLD 0xA0B4 3420 #define GEN6_RC6_THRESHOLD 0xA0B8 3421 #define GEN6_RC6p_THRESHOLD 0xA0BC 3422 #define GEN6_RC6pp_THRESHOLD 0xA0C0 3423 #define GEN6_PMINTRMSK 0xA168 3424 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 3425 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC 3426 #define GEN6_PMIER 0x4402C 3427 #define GEN6_PMIMR 0x44024 /* rps_lock */ 3428 #define GEN6_PMINTRMSK 0xA168 3429 3430 /* Haswell-related items */ 3431 3432 /* HSW Power Wells */ 3433 #define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */ 3434 #define HSW_PWR_WELL_CTL2 0x45404 /* Driver */ 3435 #define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */ 3436 #define HSW_PWR_WELL_CTL4 0x4540C /* Debug */ 3437 #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) 3438 #define HSW_PWR_WELL_STATE_ENABLED (1<<30) 3439 #define HSW_PWR_WELL_CTL5 0x45410 3440 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) 3441 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) 3442 #define HSW_PWR_WELL_FORCE_ON (1<<19) 3443 #define HSW_PWR_WELL_CTL6 0x45414 3444 3445 /* Per-pipe DDI Function Control */ 3446 #define PIPE_DDI_FUNC_CTL_A 0x60400 3447 #define PIPE_DDI_FUNC_CTL_B 0x61400 3448 #define PIPE_DDI_FUNC_CTL_C 0x62400 3449 #define PIPE_DDI_FUNC_CTL_EDP 0x6F400 3450 #define DDI_FUNC_CTL(pipe) _PIPE(pipe, \ 3451 PIPE_DDI_FUNC_CTL_A, \ 3452 PIPE_DDI_FUNC_CTL_B) 3453 #define PIPE_DDI_FUNC_ENABLE (1<<31) 3454 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 3455 #define PIPE_DDI_PORT_MASK (0xf<<28) 3456 #define PIPE_DDI_SELECT_PORT(x) ((x)<<28) 3457 #define PIPE_DDI_MODE_SELECT_HDMI (0<<24) 3458 #define PIPE_DDI_MODE_SELECT_DVI (1<<24) 3459 #define PIPE_DDI_MODE_SELECT_DP_SST (2<<24) 3460 #define PIPE_DDI_MODE_SELECT_DP_MST (3<<24) 3461 #define PIPE_DDI_MODE_SELECT_FDI (4<<24) 3462 #define PIPE_DDI_BPC_8 (0<<20) 3463 #define PIPE_DDI_BPC_10 (1<<20) 3464 #define PIPE_DDI_BPC_6 (2<<20) 3465 #define PIPE_DDI_BPC_12 (3<<20) 3466 #define PIPE_DDI_BFI_ENABLE (1<<4) 3467 #define PIPE_DDI_PORT_WIDTH_X1 (0<<1) 3468 #define PIPE_DDI_PORT_WIDTH_X2 (1<<1) 3469 #define PIPE_DDI_PORT_WIDTH_X4 (3<<1) 3470 3471 /* DisplayPort Transport Control */ 3472 #define DP_TP_CTL_A 0x64040 3473 #define DP_TP_CTL_B 0x64140 3474 #define DP_TP_CTL_C 0x64240 3475 #define DP_TP_CTL_D 0x64340 3476 #define DP_TP_CTL_E 0x64440 3477 #define DP_TP_CTL_ENABLE (1<<31) 3478 #define DP_TP_CTL_MODE_SST (0<<27) 3479 #define DP_TP_CTL_MODE_MST (1<<27) 3480 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) 3481 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) 3482 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) 3483 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) 3484 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) 3485 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) 3486 3487 /* DisplayPort Transport Status */ 3488 #define DP_TP_STATUS_A 0x64044 3489 #define DP_TP_STATUS_B 0x64144 3490 #define DP_TP_STATUS_C 0x64244 3491 #define DP_TP_STATUS_D 0x64344 3492 #define DP_TP_STATUS_E 0x64444 3493 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) 3494 3495 /* DDI Buffer Control */ 3496 #define DDI_BUF_CTL_A 0x64000 3497 #define DDI_BUF_CTL_B 0x64100 3498 #define DDI_BUF_CTL_C 0x64200 3499 #define DDI_BUF_CTL_D 0x64300 3500 #define DDI_BUF_CTL_E 0x64400 3501 #define DDI_BUF_CTL_ENABLE (1<<31) 3502 #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ 3503 #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */ 3504 #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */ 3505 #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */ 3506 #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */ 3507 #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */ 3508 #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */ 3509 #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ 3510 #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ 3511 #define DDI_BUF_EMP_MASK (0xf<<24) 3512 #define DDI_BUF_IS_IDLE (1<<7) 3513 #define DDI_PORT_WIDTH_X1 (0<<1) 3514 #define DDI_PORT_WIDTH_X2 (1<<1) 3515 #define DDI_PORT_WIDTH_X4 (3<<1) 3516 #define DDI_INIT_DISPLAY_DETECTED (1<<0) 3517 3518 /* LPT PIXCLK_GATE */ 3519 #define PIXCLK_GATE 0xC6020 3520 #define PIXCLK_GATE_UNGATE 1<<0 3521 #define PIXCLK_GATE_GATE 0<<0 3522 3523 /* SPLL */ 3524 #define SPLL_CTL 0x46020 3525 #define SPLL_PLL_ENABLE (1<<31) 3526 #define SPLL_PLL_SCC (1<<28) 3527 #define SPLL_PLL_NON_SCC (2<<28) 3528 #define SPLL_PLL_FREQ_810MHz (0<<26) 3529 #define SPLL_PLL_FREQ_1350MHz (1<<26) 3530 3531 /* WRPLL */ 3532 #define WRPLL_CTL1 0x46040 3533 #define WRPLL_CTL2 0x46060 3534 #define WRPLL_PLL_ENABLE (1<<31) 3535 #define WRPLL_PLL_SELECT_SSC (0x01<<28) 3536 #define WRPLL_PLL_SELECT_NON_SCC (0x02<<28) 3537 #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28) 3538 /* WRPLL divider programming */ 3539 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) 3540 #define WRPLL_DIVIDER_POST(x) ((x)<<8) 3541 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) 3542 3543 /* Port clock selection */ 3544 #define PORT_CLK_SEL_A 0x46100 3545 #define PORT_CLK_SEL_B 0x46104 3546 #define PORT_CLK_SEL_C 0x46108 3547 #define PORT_CLK_SEL_D 0x4610C 3548 #define PORT_CLK_SEL_E 0x46110 3549 #define PORT_CLK_SEL_LCPLL_2700 (0<<29) 3550 #define PORT_CLK_SEL_LCPLL_1350 (1<<29) 3551 #define PORT_CLK_SEL_LCPLL_810 (2<<29) 3552 #define PORT_CLK_SEL_SPLL (3<<29) 3553 #define PORT_CLK_SEL_WRPLL1 (4<<29) 3554 #define PORT_CLK_SEL_WRPLL2 (5<<29) 3555 3556 /* Pipe clock selection */ 3557 #define PIPE_CLK_SEL_A 0x46140 3558 #define PIPE_CLK_SEL_B 0x46144 3559 #define PIPE_CLK_SEL_C 0x46148 3560 /* For each pipe, we need to select the corresponding port clock */ 3561 #define PIPE_CLK_SEL_DISABLED (0x0<<29) 3562 #define PIPE_CLK_SEL_PORT(x) ((x+1)<<29) 3563 3564 /* LCPLL Control */ 3565 #define LCPLL_CTL 0x130040 3566 #define LCPLL_PLL_DISABLE (1<<31) 3567 #define LCPLL_PLL_LOCK (1<<30) 3568 #define LCPLL_CD_CLOCK_DISABLE (1<<25) 3569 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) 3570 3571 /* Pipe WM_LINETIME - watermark line time */ 3572 #define WM_PIPE_A 0x45100 3573 #define WM_PIPE_B 0x45104 3574 #define WM_PIPE_C 0x45200 3575 #define WM_LP1 0x45108 3576 #define WM_LP2 0x4510C 3577 #define WM_LP3 0x45110 3578 #define WM_LP1_SPR 0x45120 3579 #define WM_LP2_SPR 0x45124 3580 #define WM_LP3_SPR 0x45128 3581 #define WM_MISC 0x45260 3582 #define WM_SR_CNT 0x45264 3583 #define WM_DBG 0x45280 3584 #define PIPE_WM_LINETIME_A 0x45270 3585 #define PIPE_WM_LINETIME_B 0x45274 3586 #define PIPE_WM_LINETIME_C 0x45278 3587 #define PIPE_WM_LINETIME_MASK (0x1ff) 3588 #define PIPE_WM_LINETIME_TIME(x) ((x)) 3589 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) 3590 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) 3591 3592 /* SFUSE_STRAP */ 3593 #define SFUSE_STRAP 0xc2014 3594 #define SFUSE_STRAP_DDIB_DETECTED (1<<2) 3595 #define SFUSE_STRAP_DDIC_DETECTED (1<<1) 3596 #define SFUSE_STRAP_DDID_DETECTED (1<<0) 3597 3598 /* Valleyview related items */ 3599 #define VLV_DISPLAY_BASE 0x180000 3600 3601 /* 3602 * IOSF sideband 3603 */ 3604 #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100) 3605 #define IOSF_DEVFN_SHIFT 24 3606 #define IOSF_OPCODE_SHIFT 16 3607 #define IOSF_PORT_SHIFT 8 3608 #define IOSF_BYTE_ENABLES_SHIFT 4 3609 #define IOSF_BAR_SHIFT 1 3610 #define IOSF_SB_BUSY (1<<0) 3611 #define IOSF_PORT_BUNIT 0x3 3612 #define IOSF_PORT_PUNIT 0x4 3613 #define IOSF_PORT_NC 0x11 3614 #define IOSF_PORT_DPIO 0x12 3615 #define IOSF_PORT_DPIO_2 0x1a 3616 #define IOSF_PORT_GPIO_NC 0x13 3617 #define IOSF_PORT_CCK 0x14 3618 #define IOSF_PORT_CCU 0xA9 3619 #define IOSF_PORT_GPS_CORE 0x48 3620 #define IOSF_PORT_FLISDSI 0x1B 3621 #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104) 3622 #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108) 3623 3624 #endif /* _I810_REG_H */ 3625