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Searched refs:TempRegID (Results 1 – 14 of 14) sorted by relevance

/external/llvm-project/llvm/test/TableGen/
DGlobalISelEmitterSubreg.td50 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
52 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegStat…
56 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
69 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
70 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
72 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegStat…
75 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegStat…
76 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
84 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
103 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
[all …]
DGlobalISelEmitterRegSequence.td42 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
43 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
45 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
49 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
54 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
56 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
69 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
70 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
72 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
DGlobalISelEmitter-nested-subregs.td41 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
44 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
47 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
48 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
56 // CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, MyTarget::lo…
DGlobalISelEmitter-input-discard.td19 // GISEL-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21 // GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
25 // GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
DGlobalISelEmitter-output-discard.td16 // GISEL-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
19 // GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|R…
DDefaultOpsGlobalISel.td80 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
82 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
89 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
DGlobalISelEmitter.td286 // R19C-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
288 // R19C-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
299 // R19C-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenGlobalISel.inc3384 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3385 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3386 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3387 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3389 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
3393 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
3394 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
3398 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
3399 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
3402 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc2582 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
2583 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1,
2584 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1,
2586 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
2590 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
2594 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
2595 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
2596 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
2600 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
2616 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1,
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenGlobalISel.inc1445 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
1447 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1453 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1480 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
1482 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1488 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1529 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
1531 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
1537 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
1564 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenGlobalISel.inc2675 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
2677 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
2684 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3296 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3298 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
3305 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3493 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3495 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
3502 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4097 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DInstructionSelectorImpl.h864 int64_t TempRegID = MatchTable[CurrentIdx++]; in executeMatchTable() local
867 OutMIs[InsnID].addReg(State.TempRegisters[TempRegID], TempRegFlags); in executeMatchTable()
870 << InsnID << "], TempRegisters[" << TempRegID in executeMatchTable()
1035 int64_t TempRegID = MatchTable[CurrentIdx++]; in executeMatchTable() local
1038 State.TempRegisters[TempRegID] = in executeMatchTable()
1041 dbgs() << CurrentIdx << ": TempRegs[" << TempRegID in executeMatchTable()
/external/llvm-project/llvm/utils/TableGen/
DGlobalISelEmitter.cpp2775 unsigned TempRegID; member in __anon0a286f430111::TempRegRenderer
2781 TempRegRenderer(unsigned InsnID, unsigned TempRegID, bool IsDef = false, in TempRegRenderer() argument
2784 : OperandRenderer(OR_Register), InsnID(InsnID), TempRegID(TempRegID), in TempRegRenderer()
2799 << MatchTable::Comment("TempRegID") << MatchTable::IntValue(TempRegID) in emitRenderOpcodes()
3168 unsigned TempRegID; member in __anon0a286f430111::MakeTempRegisterAction
3171 MakeTempRegisterAction(const LLTCodeGen &Ty, unsigned TempRegID) in MakeTempRegisterAction() argument
3172 : Ty(Ty), TempRegID(TempRegID) { in MakeTempRegisterAction()
3178 << MatchTable::Comment("TempRegID") << MatchTable::IntValue(TempRegID) in emitActionOpcodes()
4389 unsigned TempRegID = Rule.allocateTempRegID(); in importExplicitUseRenderer() local
4391 InsertPt, *OpTy, TempRegID); in importExplicitUseRenderer()
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/external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DInstructionSelectorImpl.h934 int64_t TempRegID = MatchTable[CurrentIdx++]; in executeMatchTable() local
942 OutMIs[InsnID].addReg(State.TempRegisters[TempRegID], TempRegFlags, SubReg); in executeMatchTable()
945 << InsnID << "], TempRegisters[" << TempRegID in executeMatchTable()
1113 int64_t TempRegID = MatchTable[CurrentIdx++]; in executeMatchTable() local
1116 State.TempRegisters[TempRegID] = in executeMatchTable()
1119 dbgs() << CurrentIdx << ": TempRegs[" << TempRegID in executeMatchTable()