| /external/webrtc/modules/third_party/fft/ |
| D | fft.h | 39 double Tmp0[FFT_MAXFFTSIZE]; member
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| D | fft.c | 339 Rtmp = (REAL *) fftstate->Tmp0; in FFTRADIX()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 3609 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchBEXTRFromAndImm() local
3610 if (tryFoldLoad(Node, N0.getNode(), Input, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in matchBEXTRFromAndImm()
3612 Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Control, Input.getOperand(0)}; in matchBEXTRFromAndImm()
3645 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPISTR() local
3646 if (MayFoldLoad && tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPISTR()
3647 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPISTR()
3678 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPESTR() local
3679 if (MayFoldLoad && tryFoldLoad(Node, N2, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPESTR()
3680 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPESTR()
4226 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Load; in tryVPTESTM() local
[all …]
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| /external/llvm-project/clang/test/CodeGenOpenCL/ |
| D | amdgpu-debug-info-variable-expression.cl | 63 private int *Tmp0;
77 private int *FuncVar3 = Tmp0;
109 private int *local FuncVar13; FuncVar13 = Tmp0;
125 private int *private FuncVar18 = Tmp0;
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 3708 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchBEXTRFromAndImm() local
3709 if (tryFoldLoad(Node, N0.getNode(), Input, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in matchBEXTRFromAndImm()
3711 Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Control, Input.getOperand(0)}; in matchBEXTRFromAndImm()
3744 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPISTR() local
3745 if (MayFoldLoad && tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPISTR()
3746 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPISTR()
3777 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPESTR() local
3778 if (MayFoldLoad && tryFoldLoad(Node, N2, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPESTR()
3779 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPESTR()
4030 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchVPTERNLOG() local
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUPromoteAlloca.cpp | 709 Value *Tmp0 = Builder.CreateMul(TCntY, TCntZ, "", true, true); in handleAlloca() local
710 Tmp0 = Builder.CreateMul(Tmp0, TIdX); in handleAlloca()
712 Value *TID = Builder.CreateAdd(Tmp0, Tmp1); in handleAlloca()
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| D | AMDGPUISelLowering.cpp | 1460 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT), in LowerUDIVREM() local
1464 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num); in LowerUDIVREM()
1676 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not); in LowerFTRUNC() local
1686 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC()
1783 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M); in LowerFROUND64() local
1785 DAG.getConstant(0, SL, MVT::i64), Tmp0, in LowerFROUND64()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUPromoteAlloca.cpp | 815 Value *Tmp0 = Builder.CreateMul(TCntY, TCntZ, "", true, true); in handleAlloca() local
816 Tmp0 = Builder.CreateMul(Tmp0, TIdX); in handleAlloca()
818 Value *TID = Builder.CreateAdd(Tmp0, Tmp1); in handleAlloca()
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| D | AMDGPUCodeGenPrepare.cpp | 825 Value *Tmp0 = Builder.CreateSelect(RCP_HI_0_CC, RCP_A_E, RCP_S_E); in expandDivRem32() local
828 Value *Quotient = getMulHu(Builder, Tmp0, Num); in expandDivRem32()
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| D | AMDGPUISelLowering.cpp | 1896 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT), in LowerUDIVREM() local
1900 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num); in LowerUDIVREM()
2112 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not); in LowerFTRUNC() local
2122 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC()
2225 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M); in LowerFROUND64() local
2227 DAG.getConstant(0, SL, MVT::i64), Tmp0, in LowerFROUND64()
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| D | AMDGPULegalizerInfo.cpp | 1463 auto Tmp0 = B.buildAnd(S64, Src, Not); in legalizeIntrinsicTrunc() local
1469 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0); in legalizeIntrinsicTrunc()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUPromoteAlloca.cpp | 960 Value *Tmp0 = Builder.CreateMul(TCntY, TCntZ, "", true, true); in handleAlloca() local
961 Tmp0 = Builder.CreateMul(Tmp0, TIdX); in handleAlloca()
963 Value *TID = Builder.CreateAdd(Tmp0, Tmp1); in handleAlloca()
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| D | AMDGPULegalizerInfo.cpp | 1983 auto Tmp0 = B.buildAnd(S64, Src, Not); in legalizeIntrinsicTrunc() local
1989 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0); in legalizeIntrinsicTrunc()
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| D | AMDGPUISelLowering.cpp | 2180 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not); in LowerFTRUNC() local
2190 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC()
|
| /external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/ |
| D | supernode.ll | 270 ; Tmp0 = A0 + 2.0
276 ; S[0] = Tmp0 + B0
313 %Tmp0 = fadd fast double %A0, 2.0
321 %Sum0 = fadd fast double %Tmp0, %B0
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2211 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
2212 bool foldedLoad = tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2215 foldedLoad = tryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2227 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), in Select()
2364 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
2365 bool foldedLoad = tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2372 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain; in Select() local
2373 if (tryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in Select()
2374 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) }; in Select()
2428 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), in Select()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 387 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
388 Tmp0 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); in LowerFPToInt()
399 Tmp0 = InReg; in LowerFPToInt()
401 BuildMI(BB, DL, TII.get(Abs), Tmp0).addReg(InReg); in LowerFPToInt()
405 BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
415 BuildMI(BB, DL, TII.get(GE), SecondCmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
|
| /external/llvm-project/llvm/lib/Transforms/Utils/ |
| D | IntegerDivision.cpp | 254 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True}); in generateUnsignedDivisionCode() local
256 Value *SR = Builder.CreateSub(Tmp0, Tmp1); in generateUnsignedDivisionCode()
|
| /external/llvm/lib/Transforms/Utils/ |
| D | IntegerDivision.cpp | 255 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True}); in generateUnsignedDivisionCode() local
257 Value *SR = Builder.CreateSub(Tmp0, Tmp1); in generateUnsignedDivisionCode()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Utils/ |
| D | IntegerDivision.cpp | 254 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True}); in generateUnsignedDivisionCode() local
256 Value *SR = Builder.CreateSub(Tmp0, Tmp1); in generateUnsignedDivisionCode()
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| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 377 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
378 Tmp0 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); in LowerFPToInt()
389 Tmp0 = InReg; in LowerFPToInt()
391 BuildMI(BB, DL, TII.get(Abs), Tmp0).addReg(InReg); in LowerFPToInt()
395 BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
405 BuildMI(BB, DL, TII.get(GE), SecondCmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 4244 SDValue Tmp0 = Op.getOperand(0); in LowerFCOPYSIGN() local
4249 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || in LowerFCOPYSIGN()
4250 Tmp0.getOpcode() == ARMISD::VMOVDRR; in LowerFCOPYSIGN()
4264 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); in LowerFCOPYSIGN()
4275 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); in LowerFCOPYSIGN()
4286 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot)); in LowerFCOPYSIGN()
4309 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFCOPYSIGN()
4310 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); in LowerFCOPYSIGN()
4312 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); in LowerFCOPYSIGN()
4316 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 5502 SDValue Tmp0 = Op.getOperand(0); in LowerFCOPYSIGN() local
5507 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || in LowerFCOPYSIGN()
5508 Tmp0.getOpcode() == ARMISD::VMOVDRR; in LowerFCOPYSIGN()
5522 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); in LowerFCOPYSIGN()
5533 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); in LowerFCOPYSIGN()
5544 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot)); in LowerFCOPYSIGN()
5567 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFCOPYSIGN()
5568 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); in LowerFCOPYSIGN()
5570 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); in LowerFCOPYSIGN()
5574 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
[all …]
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 5749 SDValue Tmp0 = Op.getOperand(0); in LowerFCOPYSIGN() local
5754 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || in LowerFCOPYSIGN()
5755 Tmp0.getOpcode() == ARMISD::VMOVDRR; in LowerFCOPYSIGN()
5769 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); in LowerFCOPYSIGN()
5780 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); in LowerFCOPYSIGN()
5791 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot)); in LowerFCOPYSIGN()
5814 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFCOPYSIGN()
5815 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); in LowerFCOPYSIGN()
5817 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); in LowerFCOPYSIGN()
5821 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
[all …]
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 6182 SDValue Tmp0 = getValue(I.getArgOperand(0)); in visitBinaryFloatCall() local
6184 EVT VT = Tmp0.getValueType(); in visitBinaryFloatCall()
6185 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1)); in visitBinaryFloatCall()
|