Searched refs:UFS_SYS_PHY_CLK_CTRL_REG (Results 1 – 3 of 3) sorted by relevance
114 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()116 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); in hikey960_ufs_reset()124 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()142 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); in hikey960_ufs_reset()145 mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); in hikey960_ufs_reset()146 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); in hikey960_ufs_reset()
89 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()91 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); in hikey960_ufs_reset()99 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()117 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); in hikey960_ufs_reset()120 mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); in hikey960_ufs_reset()121 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); in hikey960_ufs_reset()
321 #define UFS_SYS_PHY_CLK_CTRL_REG (UFS_SYS_REG_BASE + 0x010) macro